Temporal logic verification using simulation

Georgios E. Fainekos, Antoine Girard, George J. Pappas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

35 Scopus citations

Abstract

In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the verification of the temporal properties of a continuous system by verifying only a finite number of its (simulated) trajectories. The proposed framework comprises two main ideas. First, we take advantage of the fact that in metric spaces we can quantify how close are two different states. Based on that, we define robust, multi-valued semantics for MTL (and LTL) formulas. These capture not only the usual Boolean satisfiability of the formula, but also topological information regarding the distance from unsatisfiability. Second, we use the recently developed notion of bisimulation functions to infer the behavior of a set of trajectories that lie in the neighborhood of the simulated one. If the latter set of trajectories is bounded by the tube of robustness, then we can infer that all the trajectories in the neighborhood of the simulated one satisfy the same temporal specification as the simulated trajectory. The interesting and promising feature of our approach is that the more robust the system is with respect to the temporal logic specification, the less is the number of simulations that are required in order to verify the system.

Original languageEnglish (US)
Title of host publicationFormal Modeling and Analysis of Timed Systems - 4th International Conference, FORMATS 2006, Proceedings
PublisherSpringer Verlag
Pages171-186
Number of pages16
ISBN (Print)3540450262, 9783540450269
DOIs
StatePublished - 2006
Event4th International Conference on Formal Modeling and Analysis of Timed Systems, FORMATS 2006 - Paris, France
Duration: Sep 25 2006Sep 27 2006

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4202 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other4th International Conference on Formal Modeling and Analysis of Timed Systems, FORMATS 2006
CountryFrance
CityParis
Period9/25/069/27/06

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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    Fainekos, G. E., Girard, A., & Pappas, G. J. (2006). Temporal logic verification using simulation. In Formal Modeling and Analysis of Timed Systems - 4th International Conference, FORMATS 2006, Proceedings (pp. 171-186). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4202 LNCS). Springer Verlag. https://doi.org/10.1007/11867340_13