TY - GEN
T1 - Temperature and process variations aware power gating of functional units
AU - Kannan, Deepa
AU - Shrivastava, Aviral
AU - Mohan, Vipin
AU - Bhardwaj, Sarvesh
AU - Vrudhula, Sarma
PY - 2008/7/25
Y1 - 2008/7/25
N2 - Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Integer ALUs are regions of high power density and significantly contribute to the variation in the whole processor power consumption. Hence, it is important to reduce both the power consumption and the variation in power consumption of the FUs. Among existing FU power reduction techniques, power gating (PG) has been most effective. In this paper, we introduce a leakage sensor inside the FUs and propose a temperature and process variation aware power gating scheme, Leakage Aware Power Gating (LA-PG). Our experimental results demonstrate that LA-PG results in 22% reduction in mean and a 25% reduction in standard deviation of the ALU energy consumption when compared to existing power gating techniques, without significant performance penalty.
AB - Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Integer ALUs are regions of high power density and significantly contribute to the variation in the whole processor power consumption. Hence, it is important to reduce both the power consumption and the variation in power consumption of the FUs. Among existing FU power reduction techniques, power gating (PG) has been most effective. In this paper, we introduce a leakage sensor inside the FUs and propose a temperature and process variation aware power gating scheme, Leakage Aware Power Gating (LA-PG). Our experimental results demonstrate that LA-PG results in 22% reduction in mean and a 25% reduction in standard deviation of the ALU energy consumption when compared to existing power gating techniques, without significant performance penalty.
UR - http://www.scopus.com/inward/record.url?scp=47649120563&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=47649120563&partnerID=8YFLogxK
U2 - 10.1109/VLSI.2008.83
DO - 10.1109/VLSI.2008.83
M3 - Conference contribution
AN - SCOPUS:47649120563
SN - 0769530834
SN - 9780769530833
T3 - Proceedings of the IEEE International Frequency Control Symposium and Exposition
SP - 515
EP - 520
BT - Proceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008
T2 - 21st International Conference on VLSI Design, VLSI DESIGN 2008
Y2 - 4 January 2008 through 8 January 2008
ER -