Technology Mapping for Threshold and Logic Gate Hybrid Circuits

The study of threshold functions dates back to the 1960s and an extensive body of literature exists on the subject. The advent of nanotechnology has renewed interest in threshold logic because several nano-devices such as resonant tunneling diodes (RTDs) and quantum cellular automata (QCAs) are inherently threshold gates. Since not all Boolean functions are threshold, an essential computation in the threshold logic synthesis is to determine whether or not a given Boolean function is a threshold function. Until recently this was done by solving an integer linear program (ILP). This approach is practical only for functions with small support sets and cannot be used when exploring a large gate level netlist for threshold functions. New methods based on differential logic such as DCSTL and SCSDL have been the most promising because they employ the conventional CMOS devices, require no special processing and have been shown to be very fast and low power. Unfortunately, the existing differential logic architectures are highly susceptible to failure due to noise and sizing them to achieve the same level of noise margin TLL makes their power and delay unacceptably high. Researchers at Arizona State University have developed the design of a standard cell library of threshold gates called Differential mode Threshold Gates (DTG) using a differential mode architecture and a functional decomposition method to map arbitrary Boolean functions using DTGs. The technology mapped netlist consists of both conventional CMOS logic cells and DTGs and is referred to as a hybrid circuit. The proposed decomposition technique produces hybrid circuits that have up to 36% less dynamic power, about 50% less leakage power and around 38% less area, post place and routing using a commercial 65 nm LP (low power) library, operated at the same (peak) frequency as the optimized conventional CMOS implementation. Potential Applications Semiconductor Companies A Very Large Industry Benefits and Advantages Significantly reduced levels of dynamic power up to 36% less Considerably reduced circuit area up to 38% less area required Less power leakage up to 50% less High Performance Maintains same levels of high performance as CMOS counterparts Download Original PDF