Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip

Pai Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

46 Scopus citations

Abstract

Technology-design co-optimization methodologies of the resistive cross-point array are proposed for implementing the machine learning algorithms on a chip. A novel read and write scheme is designed to accelerate the training process, which realizes fully parallel operations of the weighted sum and the weight update. Furthermore, technology and design parameters of the resistive cross-point array are co-optimized to enhance the learning accuracy, latency and energy consumption, etc. In contrast to the conventional memory design, a set of reverse scaling rules is proposed on the resistive cross-point array to achieve high learning accuracy. These include 1) larger wire width to reduce the IR drop on interconnects thereby increasing the learning accuracy; 2) use of multiple cells for each weight element to alleviate the impact of the device variations, at an affordable expense of area, energy and latency. The optimized resistive cross-point array with peripheral circuitry is implemented at the 65 nm node. Its performance is benchmarked for handwritten digit recognition on the MNIST database using gradient-based sparse coding. Compared to state-of-the-art software approach running on CPU, it achieves >103 speed-up and >106 energy efficiency improvement, enabling real-time image feature extraction and learning.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages854-859
Number of pages6
Volume2015-April
ISBN (Print)9783981537048
StatePublished - Apr 22 2015
Event2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 - Grenoble, France
Duration: Mar 9 2015Mar 13 2015

Other

Other2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
CountryFrance
CityGrenoble
Period3/9/153/13/15

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Keywords

  • cross-point array
  • machine learning
  • neuromorphic computing
  • resistive memory
  • synaptic device

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Chen, P. Y., Kadetotad, D., Xu, Z., Mohanty, A., Lin, B., Ye, J., Vrudhula, S., Seo, J., Cao, Y., & Yu, S. (2015). Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. In Proceedings -Design, Automation and Test in Europe, DATE (Vol. 2015-April, pp. 854-859). [7092504] Institute of Electrical and Electronics Engineers Inc..