Techniques for estimating test length under random test

Amitava Majumdar, Sarma B.K. Vrudhula

Research output: Contribution to journalArticlepeer-review


When a circuit is tested using random or pseudorandom patterns, it is essential to determine the amount of time (test length) required to test it adequately. We present a methodology for predicting different statistics of random pattern test length. While earlier methods allowed estimation only of upper bounds of test length and only for exhaustive fault coverage, the technique presented here is capable of providing estimates of all statistics of interest (including expected value and variance) for all coverage specifications. Our methodology is based on sampling models developed for fault coverage estimation [1]. Test length is viewed as a waiting time on fault coverage. Based on this relation we derive the distribution of test length as a function of fault coverage. Methods of approximating expected value and variance of test length are presented. Accuracy of these approximations can be controlled by the user. A practical technique for predicting expected test length is developed. This technique is based on clustering faults into equal detectability subsets. A simple and effective algorithm for fault clustering is also presented. The sampling model is applied to each cluster independently and the results are then aggregated to yield test lengths for the whole circuit. Results of experiments with several circuits (both ISCAS '85 benchmarks and other practical circuits) are also provided.

Original languageEnglish (US)
Pages (from-to)285-297
Number of pages13
JournalJournal of Electronic Testing
Issue number2-3
StatePublished - May 1 1994


  • Circuit testing
  • test quality
  • urn models
  • waiting time distribution

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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