HfO2 based high-κ metal gate (HKMG) transistors offer low leakage current and high integration density. However, they are vulnerable to defect formation. In this paper, we have demonstrated a Büttiker probe based leakage current model  for determining the gate leakage current in a HKMG transistor due to defects in the gate dielectric layer. These defects can be pre-existing defects (PEDs) as well as the stress induced defects in the gate dielectric stack. The model was also used to determine the post breakdown gate current characteristics. We have verified our model with experimentally measured data from 28nm planar devices with HfSiON/SiO2 gate dielectric layer. In addition, we have integrated the Büttiker probe method and percolation model  to predict the time to failure (tBD) of the device. The proposed simulation methodology can also be used to determine the required stress condition (SC) to observe breakdown in a device within a certain period of time.