Abstract

This paper proposes the design of a tool that automates the generation of the target architecture onto which reconfigurable logic blocks are mapped. The target architecture is hierarchical in nature and includes both the number and complexity of the interconnect switches at each level. The architecture is generated based on our proposed vector space model for representing interconnections between reconfigurable blocks. The automation is based on our modified version of constrained agglomerative hierarchical clustering that has been proven as the best hierarchical clustering approach in the field of data mining. The proposed architecture optimizes both transient and static power while meeting timing constraints.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
EditorsT.P. Plaks
Pages315
Number of pages1
StatePublished - 2004
EventProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 - Las Vegas, NV, United States
Duration: Jun 21 2004Jun 24 2004

Other

OtherProceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
CountryUnited States
CityLas Vegas, NV
Period6/21/046/24/04

Fingerprint

Vector spaces
Data mining
Automation
Switches

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Srinivasan, M., & Panchanathan, S. (2004). Target architecture automation for reconfigurable logic blocks. In T. P. Plaks (Ed.), Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04 (pp. 315)

Target architecture automation for reconfigurable logic blocks. / Srinivasan, Mayur; Panchanathan, Sethuraman.

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. ed. / T.P. Plaks. 2004. p. 315.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Srinivasan, M & Panchanathan, S 2004, Target architecture automation for reconfigurable logic blocks. in TP Plaks (ed.), Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. pp. 315, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, Las Vegas, NV, United States, 6/21/04.
Srinivasan M, Panchanathan S. Target architecture automation for reconfigurable logic blocks. In Plaks TP, editor, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. 2004. p. 315
Srinivasan, Mayur ; Panchanathan, Sethuraman. / Target architecture automation for reconfigurable logic blocks. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04. editor / T.P. Plaks. 2004. pp. 315
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