TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers

Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle analog cores in a plug-and-play fashion. A test wrapper based on an ADC/DAC pair and a digital configuration circuit is designed for analog cores such that these cores can be accessed through digital TAMs. In this way, there is no dependence on an analog test bus and expensive mixed-signal testers. Experimental results are presented for several ITC'02 SOC test benchmarks to which three analog cores are added. The results show that the testing of analog cores can be interleaved with the testing of digital cores to reduce the overall testing time for a mixed-signal SOC.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Pages95-99
Number of pages5
StatePublished - 2003
Externally publishedYes
EventIEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers - San Jose, CA, United States
Duration: Nov 9 2003Nov 13 2003

Other

OtherIEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers
CountryUnited States
CitySan Jose, CA
Period11/9/0311/13/03

ASJC Scopus subject areas

  • Software

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  • Cite this

    Sehgal, A., Ozev, S., & Chakrabarty, K. (2003). TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (pp. 95-99)