Abstract
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle analog cores in a plug-and-play fashion. A test wrapper based on an ADC/DAC pair and a digital configuration circuit is designed for analog cores such that these cores can be accessed through digital TAMs. In this way, there is no dependence on an analog test bus and expensive mixed-signal testers. Experimental results are presented for several ITC'02 SOC test benchmarks to which three analog cores are added. The results show that the testing of analog cores can be interleaved with the testing of digital cores to reduce the overall testing time for a mixed-signal SOC.
Original language | English (US) |
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Title of host publication | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers |
Pages | 95-99 |
Number of pages | 5 |
State | Published - 2003 |
Externally published | Yes |
Event | IEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers - San Jose, CA, United States Duration: Nov 9 2003 → Nov 13 2003 |
Other
Other | IEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers |
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Country/Territory | United States |
City | San Jose, CA |
Period | 11/9/03 → 11/13/03 |
ASJC Scopus subject areas
- Software