TY - GEN
T1 - Systolic array architecture for real-time Gabor decomposition
AU - Iyengar, Giridharan
AU - Panchanathan, Sethuraman
PY - 1992
Y1 - 1992
N2 - In this paper, we propose a combined systolic array - content addressable memory architecture for image compression using Gabor decomposition. Gabor decomposition is attractive for image compression since the basis functions match the human visual profiles. Gabor functions also achieve the lowest bound on the joint entropy of data. However these functions are not orthogonal and hence an analytic solution for the decomposition does not exist. Recently it has been shown that Gabor decomposition can be computed as a multiplication between a transform matrix and a vector of image data. Systolic arrays are attractive for matrix multiplication problems and content addressable memories (CAM) offer fast means of data access. For an n × n image, the proposed architecture for Gabor decomposition consists of a linear systolic array of n processing elements each with a local CAM. Simulations and complexity studies show that this architecture can achieve real-time performance with current technology. This architecture is modular and regular and hence it can be implemented in VLSI as a codec.
AB - In this paper, we propose a combined systolic array - content addressable memory architecture for image compression using Gabor decomposition. Gabor decomposition is attractive for image compression since the basis functions match the human visual profiles. Gabor functions also achieve the lowest bound on the joint entropy of data. However these functions are not orthogonal and hence an analytic solution for the decomposition does not exist. Recently it has been shown that Gabor decomposition can be computed as a multiplication between a transform matrix and a vector of image data. Systolic arrays are attractive for matrix multiplication problems and content addressable memories (CAM) offer fast means of data access. For an n × n image, the proposed architecture for Gabor decomposition consists of a linear systolic array of n processing elements each with a local CAM. Simulations and complexity studies show that this architecture can achieve real-time performance with current technology. This architecture is modular and regular and hence it can be implemented in VLSI as a codec.
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M3 - Conference contribution
AN - SCOPUS:0026982262
SN - 0819410187
T3 - Proceedings of SPIE - The International Society for Optical Engineering
SP - 1006
EP - 1015
BT - Proceedings of SPIE - The International Society for Optical Engineering
PB - Publ by Int Soc for Optical Engineering
T2 - Visual Communications and Image Processing '92
Y2 - 18 November 1992 through 20 November 1992
ER -