Systolic array architecture for image coding using vector quantization

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A systolic array architecture for image coding using vector quantization (VQ) is presented. The high-speed architectures for VQ reported thus far in the literature only implement image encoding but not codebook generation. In the proposed architecture, the encoding and codebook generation operations are overlapped in the same structure. A basic systolic cell is designed with two modes (forward and reverse) of operation. In the forward mode, the cell executes the basic operation in a VQ encoder, namely, distortion computation. In the reverse mode, the cell executes the new codeword computation operation. An array of L × N cells is connected in parallel and pipeline in the directions of vector dimension, L, and codeword dimension, N, respectively. The two modes of operation take place simultaneously with a delay buffer used to synchronize the operations. The regular and iterable structure makes possible the VLSI implementation of the architecture.

Original languageEnglish (US)
Title of host publicationInt Symp VLSI Technol Sys Appl Proc Tech Pap
Editors Anon
PublisherPubl by IEEE
Pages271-275
Number of pages5
StatePublished - 1989
Externally publishedYes
EventInternational Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan
Duration: May 17 1989May 19 1989

Other

OtherInternational Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers
CityTaipei, Taiwan
Period5/17/895/19/89

Fingerprint

Systolic arrays
Vector quantization
Image coding
Pipelines

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Panchanathan, S., & Goldberg, M. (1989). Systolic array architecture for image coding using vector quantization. In Anon (Ed.), Int Symp VLSI Technol Sys Appl Proc Tech Pap (pp. 271-275). Publ by IEEE.

Systolic array architecture for image coding using vector quantization. / Panchanathan, Sethuraman; Goldberg, M.

Int Symp VLSI Technol Sys Appl Proc Tech Pap. ed. / Anon. Publ by IEEE, 1989. p. 271-275.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Panchanathan, S & Goldberg, M 1989, Systolic array architecture for image coding using vector quantization. in Anon (ed.), Int Symp VLSI Technol Sys Appl Proc Tech Pap. Publ by IEEE, pp. 271-275, International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers, Taipei, Taiwan, 5/17/89.
Panchanathan S, Goldberg M. Systolic array architecture for image coding using vector quantization. In Anon, editor, Int Symp VLSI Technol Sys Appl Proc Tech Pap. Publ by IEEE. 1989. p. 271-275
Panchanathan, Sethuraman ; Goldberg, M. / Systolic array architecture for image coding using vector quantization. Int Symp VLSI Technol Sys Appl Proc Tech Pap. editor / Anon. Publ by IEEE, 1989. pp. 271-275
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