Systolic Array Architecture for Gabor Decomposition

G. Iyengar, S. Panchanathan

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

In this brief, we propose a combined systolic array-content addressable memory architecture for real-time Gabor decomposition. We then present codec designs for Progressive Image Transmission using this architecture. Gabor decomposition is attractive for image compression since the basis functions match the human visual profiles. Gabor functions also achieve the lowest bound on the joint uncertainty of data. However these functions are not orthogonal and hence an analytic solution for the decomposition does not exist. Recently it has been shown that Gabor decomposition can be computed as a multiplication between a transform matrix and a vector of image data. For an n x n image, the proposed architecture for Gabor decomposition consists of a linear systolic array of n processing elements each with a local CAM. Simulations and complexity studies show that this architecture can achieve real-time performance with current VLSI technology.

Original languageEnglish (US)
Pages (from-to)355-359
Number of pages5
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume5
Issue number4
DOIs
StatePublished - Aug 1995
Externally publishedYes

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ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering

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