Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime factor decomposition

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53 Citations (Scopus)

Abstract

Two-dimensional systolic array implementations for computing the discrete Hartley transform (DHT) and the discrete cosine transform (DCT) when the transform size N is decomposable into mutually prime factors are proposed. The existing two-dimensional formulations for DHT and DCT are modified, and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB (most significant bit) to LSB (least significant bit) binary arithmetic.

Original languageEnglish (US)
Pages (from-to)1359-1368
Number of pages10
JournalIEEE Transactions on Computers
Volume39
Issue number11
DOIs
StatePublished - Nov 1990
Externally publishedYes

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Discrete Cosine Transform
Prime factor
Discrete cosine transforms
Systolic Array
Systolic arrays
Transform
Decomposition
Decompose
Hardware Design
Decomposable
Binary
Hardware
Unit
Formulation
Computing
Architecture

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

@article{fdb665acacde44c691cae27782171c49,
title = "Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime factor decomposition",
abstract = "Two-dimensional systolic array implementations for computing the discrete Hartley transform (DHT) and the discrete cosine transform (DCT) when the transform size N is decomposable into mutually prime factors are proposed. The existing two-dimensional formulations for DHT and DCT are modified, and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB (most significant bit) to LSB (least significant bit) binary arithmetic.",
author = "Chaitali Chakrabarti and Joseph Jaja",
year = "1990",
month = "11",
doi = "10.1109/12.61045",
language = "English (US)",
volume = "39",
pages = "1359--1368",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE Computer Society",
number = "11",

}

TY - JOUR

T1 - Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime factor decomposition

AU - Chakrabarti, Chaitali

AU - Jaja, Joseph

PY - 1990/11

Y1 - 1990/11

N2 - Two-dimensional systolic array implementations for computing the discrete Hartley transform (DHT) and the discrete cosine transform (DCT) when the transform size N is decomposable into mutually prime factors are proposed. The existing two-dimensional formulations for DHT and DCT are modified, and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB (most significant bit) to LSB (least significant bit) binary arithmetic.

AB - Two-dimensional systolic array implementations for computing the discrete Hartley transform (DHT) and the discrete cosine transform (DCT) when the transform size N is decomposable into mutually prime factors are proposed. The existing two-dimensional formulations for DHT and DCT are modified, and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB (most significant bit) to LSB (least significant bit) binary arithmetic.

UR - http://www.scopus.com/inward/record.url?scp=0025517054&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025517054&partnerID=8YFLogxK

U2 - 10.1109/12.61045

DO - 10.1109/12.61045

M3 - Article

AN - SCOPUS:0025517054

VL - 39

SP - 1359

EP - 1368

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 11

ER -