Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition

Chaitali Chakrabarti; Joseph JáJá

doi:10.1109/12.61045

Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition

Chaitali Chakrabarti, Joseph JáJá

Research output: Contribution to journal › Article › peer-review

56 Scopus citations

Abstract

This paper proposes two-dimensional systolic array implementations for computing the discrete Hartley (DHT) and the discrete cosine transforms (DCT) when the transform size A’ is decomposable into mutually prime factors. The existing two-dimensional formulations for DHT and DCT are modified and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB to LSB binary arithmetic.

Original language	English (US)
Pages (from-to)	1359-1368
Number of pages	10
Journal	IEEE Transactions on Computers
Volume	39
Issue number	11
DOIs	https://doi.org/10.1109/12.61045
State	Published - Nov 1990
Externally published	Yes

Keywords

Architecture
VLSI
bit-serial
discrete Hartley transform (DHT)
discrete cosine transform
prime-factor decomposition
systolic

ASJC Scopus subject areas

Software
Theoretical Computer Science
Hardware and Architecture
Computational Theory and Mathematics

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10.1109/12.61045

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title = "Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition",

abstract = "This paper proposes two-dimensional systolic array implementations for computing the discrete Hartley (DHT) and the discrete cosine transforms (DCT) when the transform size A{\textquoteright} is decomposable into mutually prime factors. The existing two-dimensional formulations for DHT and DCT are modified and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB to LSB binary arithmetic.",

keywords = "Architecture, VLSI, bit-serial, discrete Hartley transform (DHT), discrete cosine transform, prime-factor decomposition, systolic",

author = "Chaitali Chakrabarti and Joseph J{\'a}J{\'a}",

note = "Funding Information: Manuscript received March 4, 1988; revised May 10, 1989. This paper was supported in part by NSF Grant DCR-86-00378 and by the Systems Research Center Contract OIR-85-00108. C. Chakraharti is with the Department of Electrical Engineering and Systems Research Center, University of Maryland, College Park, MD 20742. J. Jab is with the Department of Electrical Engineering, Institute for Advanced Computer Studies and Systems Research Center, University of Maryland, College Park, MD 20742. IEEE Log Number 9037988.",

year = "1990",

month = nov,

doi = "10.1109/12.61045",

language = "English (US)",

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N1 - Funding Information: Manuscript received March 4, 1988; revised May 10, 1989. This paper was supported in part by NSF Grant DCR-86-00378 and by the Systems Research Center Contract OIR-85-00108. C. Chakraharti is with the Department of Electrical Engineering and Systems Research Center, University of Maryland, College Park, MD 20742. J. Jab is with the Department of Electrical Engineering, Institute for Advanced Computer Studies and Systems Research Center, University of Maryland, College Park, MD 20742. IEEE Log Number 9037988.

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N2 - This paper proposes two-dimensional systolic array implementations for computing the discrete Hartley (DHT) and the discrete cosine transforms (DCT) when the transform size A’ is decomposable into mutually prime factors. The existing two-dimensional formulations for DHT and DCT are modified and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB to LSB binary arithmetic.

AB - This paper proposes two-dimensional systolic array implementations for computing the discrete Hartley (DHT) and the discrete cosine transforms (DCT) when the transform size A’ is decomposable into mutually prime factors. The existing two-dimensional formulations for DHT and DCT are modified and the corresponding algorithms are mapped into two-dimensional systolic arrays. The resulting architecture is fully pipelined with no control units. The hardware design is based on bit serial left to right MSB to LSB binary arithmetic.

KW - Architecture

KW - VLSI

KW - bit-serial

KW - discrete Hartley transform (DHT)

KW - discrete cosine transform

KW - prime-factor decomposition

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Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition

Abstract

Keywords

ASJC Scopus subject areas

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