Systematic analysis of the timing and power impact of pure lines and cuts routing for multiple patterning

Vinay Vashishtha, Lovish Masand, Ankita Dosi, Chandarasekaran Ramamurthy, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Line and cut based patterning for BEOL layers is an attractive solution to address the block mask patterning challenges related to self-aligned double patterning. It also enables integrated fill, with fill as an artifact of unused metal routes following lines and cuts patterning. Traditional post-layout fill involves inserting metal at large distances to limit design impact, but is less effective at alleviating metal thickness variation due to density effects. While integrated fill reduces metal thickness variation, it has a negative impact on capacitance, delay and power dissipation. This work studies the impact of pure lines/cuts integrated fill on design performance metrics using a predictive 7 nm PDK. Two fully implemented auto-place and routed (APR) designs are considered for the experiments, one small and one large. Our comparison is from no fill to integrated fill, assuming conventional fill would not impact timing. The impact of integrated fill on capacitance and overall timing is evaluated using Calibre PEX and PrimeTime. We show these results are in line with simple "back of the envelope" estimates and simple models and are very significant for large designs.

Original languageEnglish (US)
Title of host publicationDesign-Process-Technology Co-optimization for Manufacturability XI
EditorsJason P. Cain, Luigi Capodieci
PublisherSPIE
ISBN (Electronic)9781510607477
DOIs
StatePublished - 2017
EventDesign-Process-Technology Co-optimization for Manufacturability XI 2017 - San Jose, United States
Duration: Mar 1 2017Mar 2 2017

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
Volume10148
ISSN (Print)0277-786X
ISSN (Electronic)1996-756X

Other

OtherDesign-Process-Technology Co-optimization for Manufacturability XI 2017
Country/TerritoryUnited States
CitySan Jose
Period3/1/173/2/17

Keywords

  • Automated place and route
  • Capacitance
  • Integrated fill
  • Multiple patterning

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering

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