The paper introduces the problem of system-level thermal aware design of applications with uncertain run time on an embedded processor equipped with dynamic voltage/frequency scaling features. The problem takes as inputs a task sequence, cycle time distribution of each task, and processor thermal model. The solution specifies a voltage/frequency assignment to the tasks such that the expected latency is minimized subject to the probability that the peak temperature constraint is not violated is no less than a designer specified value. We prove that the problem is at least NP-hard, and present optimal and (1 + ε) fully polynomial time approximation scheme as solutions. To the best of our knowledge, this paper is the first work that addresses the stochastic version of the system-level thermal-aware design problem. We evaluate the effectiveness of our techniques by experimenting with realistic and synthetic benchmarks.