@inproceedings{fd307f6853324af8a010a9e09966b459,
title = "System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC",
abstract = "Many embedded processor chips aimed at high performance and low power application domains are implemented as multiprocessor System-on-Chip (MPSoC) devices. The multimedia and communication sub-systems of an MPSoC perform some of the most computation intensive and performance critical tasks, and are key determinants of the system-level performance and power consumption. This paper presents an automated technique for synthesizing the system-level memory architecture (both code and data) for the streaming sub-systems of an embedded processor. The experimental results evaluate effectiveness of the proposed technique by synthesizing the system-level memory architecture for benchmark stream processing applications and comparisons against an existing approach.",
keywords = "SDF, code overlay, data minimization, memory synthesis",
author = "Glenn Leary and Weijia Che and Chatha, {Karam S.}",
year = "2012",
month = jul,
day = "11",
doi = "10.1145/2228360.2228481",
language = "English (US)",
isbn = "9781450311991",
series = "Proceedings - Design Automation Conference",
pages = "672--677",
booktitle = "Proceedings of the 49th Annual Design Automation Conference, DAC '12",
note = "49th Annual Design Automation Conference, DAC '12 ; Conference date: 03-06-2012 Through 07-06-2012",
}