System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC

Glenn Leary, Weijia Che, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Many embedded processor chips aimed at high performance and low power application domains are implemented as multiprocessor System-on-Chip (MPSoC) devices. The multimedia and communication sub-systems of an MPSoC perform some of the most computation intensive and performance critical tasks, and are key determinants of the system-level performance and power consumption. This paper presents an automated technique for synthesizing the system-level memory architecture (both code and data) for the streaming sub-systems of an embedded processor. The experimental results evaluate effectiveness of the proposed technique by synthesizing the system-level memory architecture for benchmark stream processing applications and comparisons against an existing approach.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages672-677
Number of pages6
DOIs
StatePublished - 2012
Event49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States
Duration: Jun 3 2012Jun 7 2012

Other

Other49th Annual Design Automation Conference, DAC '12
CountryUnited States
CitySan Francisco, CA
Period6/3/126/7/12

Fingerprint

Stream Processing
Memory architecture
Multiprocessor Systems
Embedded Processor
Subsystem
Synthesis
Processing
Electric power utilization
Streaming
Power Consumption
Multimedia
Communication
Determinant
Chip
High Performance
Benchmark
Evaluate
Experimental Results
Architecture
System-on-chip

Keywords

  • code overlay
  • data minimization
  • memory synthesis
  • SDF

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Leary, G., Che, W., & Chatha, K. S. (2012). System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC. In Proceedings - Design Automation Conference (pp. 672-677) https://doi.org/10.1145/2228360.2228481

System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC. / Leary, Glenn; Che, Weijia; Chatha, Karam S.

Proceedings - Design Automation Conference. 2012. p. 672-677.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Leary, G, Che, W & Chatha, KS 2012, System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC. in Proceedings - Design Automation Conference. pp. 672-677, 49th Annual Design Automation Conference, DAC '12, San Francisco, CA, United States, 6/3/12. https://doi.org/10.1145/2228360.2228481
Leary G, Che W, Chatha KS. System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC. In Proceedings - Design Automation Conference. 2012. p. 672-677 https://doi.org/10.1145/2228360.2228481
Leary, Glenn ; Che, Weijia ; Chatha, Karam S. / System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC. Proceedings - Design Automation Conference. 2012. pp. 672-677
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