System level methodology for programming CMP based multi-threaded network processor architectures

Vijaykumar Ramamurthi; Jason McCollum; Christopher Ostler; Karam S. Chatha

doi:10.1109/ISVLSI.2005.71

System level methodology for programming CMP based multi-threaded network processor architectures

Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha

Computing and Augmented Intelligence, School of (IAFSE-SCAI)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Scopus citations

Abstract

The increasing demand for programmable platforms that enable high bandwidth communication traffic processing has led to the advent of chip multi-processor (CMP) based multi-threaded network processor (NP) architectures. The CMP based architectures include a multitude of heterogeneous memory units ranging from on-chip register banks, local data memories, and scratch pads to multiple banks of off-chip SRAM and DRAM. Implementation of applications on such complex CMP architectures involves mapping of functionality on processing units, and mapping of data items on the memory units with an objective of maximizing the throughput. This paper presents a system-level methodology that consists of a programming model and optimization techniques for solving the functionality and memory mapping problem on CMP based multi-threaded NP architectures. The proposed techniques are evaluated by implementing three representative NP applications on the Intel IXP2400 processor which belongs to the class of CMP based multi-threaded architectures.

Original language	English (US)
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
Editors	A. Smailagic, N. Ranganathan
Pages	110-116
Number of pages	7
DOIs	https://doi.org/10.1109/ISVLSI.2005.71
State	Published - Oct 25 2005
Event	IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design - Tampa, FL, United States Duration: May 11 2005 → May 12 2005

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

Other

Other	IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
Country/Territory	United States
City	Tampa, FL
Period	5/11/05 → 5/12/05

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/ISVLSI.2005.71

Cite this

Ramamurthi, V., McCollum, J., Ostler, C., & Chatha, K. S. (2005). System level methodology for programming CMP based multi-threaded network processor architectures. In A. Smailagic, & N. Ranganathan (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design (pp. 110-116). (Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI). https://doi.org/10.1109/ISVLSI.2005.71

System level methodology for programming CMP based multi-threaded network processor architectures. / Ramamurthi, Vijaykumar; McCollum, Jason; Ostler, Christopher et al.

Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design. ed. / A. Smailagic; N. Ranganathan. 2005. p. 110-116 (Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ramamurthi, V, McCollum, J, Ostler, C & Chatha, KS 2005, System level methodology for programming CMP based multi-threaded network processor architectures. in A Smailagic & N Ranganathan (eds), Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design. Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI, pp. 110-116, IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design, Tampa, FL, United States, 5/11/05. https://doi.org/10.1109/ISVLSI.2005.71

Ramamurthi V, McCollum J, Ostler C, Chatha KS. System level methodology for programming CMP based multi-threaded network processor architectures. In Smailagic A, Ranganathan N, editors, Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design. 2005. p. 110-116. (Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI). doi: 10.1109/ISVLSI.2005.71

Ramamurthi, Vijaykumar ; McCollum, Jason ; Ostler, Christopher et al. / System level methodology for programming CMP based multi-threaded network processor architectures. Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design. editor / A. Smailagic ; N. Ranganathan. 2005. pp. 110-116 (Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI).

@inproceedings{048b85e3e8fa45d6ae3ff159e3e3126c,

title = "System level methodology for programming CMP based multi-threaded network processor architectures",

abstract = "The increasing demand for programmable platforms that enable high bandwidth communication traffic processing has led to the advent of chip multi-processor (CMP) based multi-threaded network processor (NP) architectures. The CMP based architectures include a multitude of heterogeneous memory units ranging from on-chip register banks, local data memories, and scratch pads to multiple banks of off-chip SRAM and DRAM. Implementation of applications on such complex CMP architectures involves mapping of functionality on processing units, and mapping of data items on the memory units with an objective of maximizing the throughput. This paper presents a system-level methodology that consists of a programming model and optimization techniques for solving the functionality and memory mapping problem on CMP based multi-threaded NP architectures. The proposed techniques are evaluated by implementing three representative NP applications on the Intel IXP2400 processor which belongs to the class of CMP based multi-threaded architectures.",

author = "Vijaykumar Ramamurthi and Jason McCollum and Christopher Ostler and Chatha, {Karam S.}",

year = "2005",

month = oct,

day = "25",

doi = "10.1109/ISVLSI.2005.71",

language = "English (US)",

isbn = "076952365X",

series = "Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI",

pages = "110--116",

editor = "A. Smailagic and N. Ranganathan",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design",

note = "IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design ; Conference date: 11-05-2005 Through 12-05-2005",

}

TY - GEN

T1 - System level methodology for programming CMP based multi-threaded network processor architectures

AU - Ramamurthi, Vijaykumar

AU - McCollum, Jason

AU - Ostler, Christopher

AU - Chatha, Karam S.

PY - 2005/10/25

Y1 - 2005/10/25

N2 - The increasing demand for programmable platforms that enable high bandwidth communication traffic processing has led to the advent of chip multi-processor (CMP) based multi-threaded network processor (NP) architectures. The CMP based architectures include a multitude of heterogeneous memory units ranging from on-chip register banks, local data memories, and scratch pads to multiple banks of off-chip SRAM and DRAM. Implementation of applications on such complex CMP architectures involves mapping of functionality on processing units, and mapping of data items on the memory units with an objective of maximizing the throughput. This paper presents a system-level methodology that consists of a programming model and optimization techniques for solving the functionality and memory mapping problem on CMP based multi-threaded NP architectures. The proposed techniques are evaluated by implementing three representative NP applications on the Intel IXP2400 processor which belongs to the class of CMP based multi-threaded architectures.

AB - The increasing demand for programmable platforms that enable high bandwidth communication traffic processing has led to the advent of chip multi-processor (CMP) based multi-threaded network processor (NP) architectures. The CMP based architectures include a multitude of heterogeneous memory units ranging from on-chip register banks, local data memories, and scratch pads to multiple banks of off-chip SRAM and DRAM. Implementation of applications on such complex CMP architectures involves mapping of functionality on processing units, and mapping of data items on the memory units with an objective of maximizing the throughput. This paper presents a system-level methodology that consists of a programming model and optimization techniques for solving the functionality and memory mapping problem on CMP based multi-threaded NP architectures. The proposed techniques are evaluated by implementing three representative NP applications on the Intel IXP2400 processor which belongs to the class of CMP based multi-threaded architectures.

UR - http://www.scopus.com/inward/record.url?scp=26844460724&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=26844460724&partnerID=8YFLogxK

U2 - 10.1109/ISVLSI.2005.71

DO - 10.1109/ISVLSI.2005.71

M3 - Conference contribution

AN - SCOPUS:26844460724

SN - 076952365X

SN - 9780769523651

T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

SP - 110

EP - 116

BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design

A2 - Smailagic, A.

A2 - Ranganathan, N.

T2 - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design

Y2 - 11 May 2005 through 12 May 2005

ER -

System level methodology for programming CMP based multi-threaded network processor architectures

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this