System level methodology for programming CMP based multi-threaded network processor architectures

Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

The increasing demand for programmable platforms that enable high bandwidth communication traffic processing has led to the advent of chip multi-processor (CMP) based multi-threaded network processor (NP) architectures. The CMP based architectures include a multitude of heterogeneous memory units ranging from on-chip register banks, local data memories, and scratch pads to multiple banks of off-chip SRAM and DRAM. Implementation of applications on such complex CMP architectures involves mapping of functionality on processing units, and mapping of data items on the memory units with an objective of maximizing the throughput. This paper presents a system-level methodology that consists of a programming model and optimization techniques for solving the functionality and memory mapping problem on CMP based multi-threaded NP architectures. The proposed techniques are evaluated by implementing three representative NP applications on the Intel IXP2400 processor which belongs to the class of CMP based multi-threaded architectures.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI
EditorsA. Smailagic, N. Ranganathan
Pages110-116
Number of pages7
DOIs
Publication statusPublished - 2005
EventIEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design - Tampa, FL, United States
Duration: May 11 2005May 12 2005

Other

OtherIEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI Design
CountryUnited States
CityTampa, FL
Period5/11/055/12/05

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Ramamurthi, V., McCollum, J., Ostler, C., & Chatha, K. S. (2005). System level methodology for programming CMP based multi-threaded network processor architectures. In A. Smailagic, & N. Ranganathan (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI (pp. 110-116) https://doi.org/10.1109/ISVLSI.2005.71