System-level design techniques for throughput and power optimization of multiprocessor SoC architectures

Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Innovative system-level computer-aided design techniques are required for optimizing the performance and power of applications that are mapped to multiprocessor system-on-chip (SoC) architectures. The paper addresses the hitherto unexplored problem of system-level low power design of multimedia and network processing applications with deadline greater than period. This paper presents four techniques that combine low power optimizations (namely dynamic voltage and frequency scaling (DVS) and dynamic power management (DPM)) with loop transformations (functional pipelining and unrolling) to minimize the power consumption, while satisfying the period and deadline constraints of the application. The strengths of the techniques lie in their low complexity and large power consumption savings when compared with existing heuristic based approaches, and close to optimum results when compared with our ILP based approach (presented elsewhere [1]). All our techniques result in large system-level power reductions when compared with existing heuristic approaches (max: 55.45%, min: 28.60 %, avg: 42.02 %). Further, the results produced by our deterministic and stochastic techniques for realistic benchmarks are on an average within 12.07 % and 4.125 %, respectively of the optimum solution produced by the ILP based approach. Our heuristic techniques are faster than the ILP based approach by several orders of magnitude.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationEmerging Trends in VLSI Systems Design
EditorsA. Smailagic, M. Bayoumi
Pages39-45
Number of pages7
DOIs
StatePublished - Sep 24 2004
EventProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design - Lafayette, LA, United States
Duration: Feb 19 2004Feb 20 2004

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Other

OtherProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
CountryUnited States
CityLafayette, LA
Period2/19/042/20/04

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Srinivasan, K., Telkar, N., Ramamurthi, V., & Chatha, K. S. (2004). System-level design techniques for throughput and power optimization of multiprocessor SoC architectures. In A. Smailagic, & M. Bayoumi (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (pp. 39-45). (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design). https://doi.org/10.1109/ISVLSI.2004.1339506