TY - JOUR
T1 - System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration
AU - Krishnan, Gokul
AU - Mandal, Sumit K.
AU - Chakrabarti, Chaitali
AU - Seo, Jae Sun
AU - Ogras, Umit
AU - Cao, Yu
N1 - Funding Information:
configuration of homogeneous RRAM-based chiplet IMC architectures (ResNet-110 on CIFAR-10). increase in tiles per chiplet due to the larger NoC size. Through this, we establish that for ResNet-110 on CIFAR-10, 16 tiles per chiplet provides near-optimal balance between NoC and NoP cost. 3.4 Simulation Time for SIAM We extract the SIAM run time on an Intel Xeon W-2133 CPU platform with 12 cores and 32GB RAM. The simulation time varies from a few minutes to a few hours for large DNNs. We report the overall simulation time for fairness. The overall simulation time includes the partitioning and mapping, circuit and NoC simulation, NoP estimation, and DRAM access estimation. ResNet-110 on CIFAR-10 takes 12 minutes while VGG-16 with 138M parameters on the ImageNet dataset takes 4.26 hours for SIAM to perform the estimation. 4. Conclusion This work presents SIAM, a novel benchmarking tool for chiplet-based IMC architectures. SIAM integrates device, circuits, architecture, NoC, NoP, and DRAM estimation. SIAM supports two different types of architectures, homogeneous and custom, across different DNNs and datasets. SIAM supports different types of chiplet-based IMC architectures, supports diverse DNN across different datasets, provides in-depth performance metrics allowing for detailed design space exploration, and has a low simulation time for benchmarking. Acknowledgments This work was supported by C-BRIC, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA. References [1] G. Krishnan, et. al, IEEE D&T, 2020. [2] S. K. Mandal, et. al, IEEE JETCAS, 2020. [3] Y. S. Shao, et. al, IEEE/ACM MICRO, 2019. [4] B. Zimmer, et. al, IEEE Symp. VLSI, 2019. [5] M-S. Lin, et. al, IEEE JSSC, 2020. [6] X. Peng, IEEE IEDM, 2019. [7] M. Jiang, et. al, IEEE ISPASS, 2013. [8] S. Sinha, IEEE DAC, 2012. [9] Y. Kim, et. al, IEEE CAL, 2015. [10] S. Ghose, et. al, ACM SIGMETRICS, 2018.
Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - In-memory computing (IMC) on a large monolithic chip for deep learning faces area, yield, and fabrication cost challenges due to the ever-increasing model sizes. 2.5D or chiplet-based architectures integrate multiple small chiplets to form a large computing system, presenting a feasible solution to accelerate large deep learning models. In this work, we present a novel benchmarking tool, SIAM, to evaluate the performance of chiplet-based IMC architectures and explore different architectural configurations. SIAM integrates device, circuit, architecture, network-on-chip (NoC), network-on-package (NoP), and DRAM access models to benchmark an end-to-end system. SIAM supports multiple deep neural networks (DNNs), different architectural configurations, and efficient design space exploration. We demonstrate the effectiveness of SIAM by benchmarking state-of-the-art DNNs across different datasets.
AB - In-memory computing (IMC) on a large monolithic chip for deep learning faces area, yield, and fabrication cost challenges due to the ever-increasing model sizes. 2.5D or chiplet-based architectures integrate multiple small chiplets to form a large computing system, presenting a feasible solution to accelerate large deep learning models. In this work, we present a novel benchmarking tool, SIAM, to evaluate the performance of chiplet-based IMC architectures and explore different architectural configurations. SIAM integrates device, circuit, architecture, network-on-chip (NoC), network-on-package (NoP), and DRAM access models to benchmark an end-to-end system. SIAM supports multiple deep neural networks (DNNs), different architectural configurations, and efficient design space exploration. We demonstrate the effectiveness of SIAM by benchmarking state-of-the-art DNNs across different datasets.
UR - http://www.scopus.com/inward/record.url?scp=85122878891&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85122878891&partnerID=8YFLogxK
U2 - 10.1109/ASICON52560.2021.9620238
DO - 10.1109/ASICON52560.2021.9620238
M3 - Conference article
AN - SCOPUS:85122878891
SN - 2162-7541
JO - Proceedings of International Conference on ASIC
JF - Proceedings of International Conference on ASIC
T2 - 14th IEEE International Conference on ASIC, ASICON 2021
Y2 - 26 October 2021 through 29 October 2021
ER -