Abstract

In this work, the single event upset susceptibility of a resistive random access memory (RRAM) system with 1-transistor-1-resistor (1T1R) and crossbar architectures to heavy ion strikes is investigated from the circuit-level to the system-level. From a circuit-level perspective, the 1T1R is only susceptible to single-bit-upset (SBU) due to the isolation of cells, while in the crossbar, multiple-bit-upsets may occur because ion-induced voltage spikes generated on drivers may propagate along rows or columns. Three factors are considered to evaluate system-level susceptibility: the upset rate, the sensitive area, and the vulnerable time window. Our analysis indicates that the crossbar architecture has a smaller maximum bit-error-rate per day as compared to the 1T1R architecture for a given sub-array size, I/O width and susceptible time window.

Original languageEnglish (US)
Article number124005
JournalSemiconductor Science and Technology
Volume31
Issue number12
DOIs
StatePublished - Nov 11 2016

Fingerprint

single event upsets
Memory architecture
random access memory
Resistors
Transistors
resistors
magnetic permeability
transistors
Heavy Ions
Networks (circuits)
Heavy ions
Bit error rate
bit error rate
spikes
Ions
Data storage equipment
isolation
heavy ions
Electric potential
electric potential

Keywords

  • 1T1R
  • bit error rate
  • crossbar
  • radiation effects
  • RRAM
  • single event upset

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Materials Chemistry
  • Electrical and Electronic Engineering

Cite this

System-level analysis of single event upset susceptibility in RRAM architectures. / Liu, Rui; Barnaby, Hugh; Yu, Shimeng.

In: Semiconductor Science and Technology, Vol. 31, No. 12, 124005, 11.11.2016.

Research output: Contribution to journalArticle

@article{b31356290bd24c4cbe478ec78edbebd4,
title = "System-level analysis of single event upset susceptibility in RRAM architectures",
abstract = "In this work, the single event upset susceptibility of a resistive random access memory (RRAM) system with 1-transistor-1-resistor (1T1R) and crossbar architectures to heavy ion strikes is investigated from the circuit-level to the system-level. From a circuit-level perspective, the 1T1R is only susceptible to single-bit-upset (SBU) due to the isolation of cells, while in the crossbar, multiple-bit-upsets may occur because ion-induced voltage spikes generated on drivers may propagate along rows or columns. Three factors are considered to evaluate system-level susceptibility: the upset rate, the sensitive area, and the vulnerable time window. Our analysis indicates that the crossbar architecture has a smaller maximum bit-error-rate per day as compared to the 1T1R architecture for a given sub-array size, I/O width and susceptible time window.",
keywords = "1T1R, bit error rate, crossbar, radiation effects, RRAM, single event upset",
author = "Rui Liu and Hugh Barnaby and Shimeng Yu",
year = "2016",
month = "11",
day = "11",
doi = "10.1088/0268-1242/31/12/124005",
language = "English (US)",
volume = "31",
journal = "Semiconductor Science and Technology",
issn = "0268-1242",
publisher = "IOP Publishing Ltd.",
number = "12",

}

TY - JOUR

T1 - System-level analysis of single event upset susceptibility in RRAM architectures

AU - Liu, Rui

AU - Barnaby, Hugh

AU - Yu, Shimeng

PY - 2016/11/11

Y1 - 2016/11/11

N2 - In this work, the single event upset susceptibility of a resistive random access memory (RRAM) system with 1-transistor-1-resistor (1T1R) and crossbar architectures to heavy ion strikes is investigated from the circuit-level to the system-level. From a circuit-level perspective, the 1T1R is only susceptible to single-bit-upset (SBU) due to the isolation of cells, while in the crossbar, multiple-bit-upsets may occur because ion-induced voltage spikes generated on drivers may propagate along rows or columns. Three factors are considered to evaluate system-level susceptibility: the upset rate, the sensitive area, and the vulnerable time window. Our analysis indicates that the crossbar architecture has a smaller maximum bit-error-rate per day as compared to the 1T1R architecture for a given sub-array size, I/O width and susceptible time window.

AB - In this work, the single event upset susceptibility of a resistive random access memory (RRAM) system with 1-transistor-1-resistor (1T1R) and crossbar architectures to heavy ion strikes is investigated from the circuit-level to the system-level. From a circuit-level perspective, the 1T1R is only susceptible to single-bit-upset (SBU) due to the isolation of cells, while in the crossbar, multiple-bit-upsets may occur because ion-induced voltage spikes generated on drivers may propagate along rows or columns. Three factors are considered to evaluate system-level susceptibility: the upset rate, the sensitive area, and the vulnerable time window. Our analysis indicates that the crossbar architecture has a smaller maximum bit-error-rate per day as compared to the 1T1R architecture for a given sub-array size, I/O width and susceptible time window.

KW - 1T1R

KW - bit error rate

KW - crossbar

KW - radiation effects

KW - RRAM

KW - single event upset

UR - http://www.scopus.com/inward/record.url?scp=84997282732&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84997282732&partnerID=8YFLogxK

U2 - 10.1088/0268-1242/31/12/124005

DO - 10.1088/0268-1242/31/12/124005

M3 - Article

AN - SCOPUS:84997282732

VL - 31

JO - Semiconductor Science and Technology

JF - Semiconductor Science and Technology

SN - 0268-1242

IS - 12

M1 - 124005

ER -