System-level analysis of single event upset susceptibility in RRAM architectures

In this work, the single event upset susceptibility of a resistive random access memory (RRAM) system with 1-transistor-1-resistor (1T1R) and crossbar architectures to heavy ion strikes is investigated from the circuit-level to the system-level. From a circuit-level perspective, the 1T1R is only susceptible to single-bit-upset (SBU) due to the isolation of cells, while in the crossbar, multiple-bit-upsets may occur because ion-induced voltage spikes generated on drivers may propagate along rows or columns. Three factors are considered to evaluate system-level susceptibility: the upset rate, the sensitive area, and the vulnerable time window. Our analysis indicates that the crossbar architecture has a smaller maximum bit-error-rate per day as compared to the 1T1R architecture for a given sub-array size, I/O width and susceptible time window.