TY - GEN
T1 - System interconnect design exploration for embedded MPSoCs
AU - Chou, Chen Ling
AU - Marculescu, Radu
AU - Ogras, Umit
AU - Chatterjee, Satrajit
AU - Kishinevsky, Michael
AU - Loukianov, Dmitrii
PY - 2011
Y1 - 2011
N2 - This paper presents a new approach for system interconnect design exploration of application-specific multi-processor systems-on-chip (MPSoCs). As a novel contribution, we develop an analytical model for network-based communication design space exploration and generate fabric solutions with optimal cost-performance trade-offs, while considering various design constrains, such as power, area, and wirelength. For large systems, we also propose an efficient approach for obtaining competitive solutions with significant less computation time compared to the exhaustive approach. The accuracy of our analytical model is validated via SystemC simulation using several synthetic applications and an industrial SoC design.
AB - This paper presents a new approach for system interconnect design exploration of application-specific multi-processor systems-on-chip (MPSoCs). As a novel contribution, we develop an analytical model for network-based communication design space exploration and generate fabric solutions with optimal cost-performance trade-offs, while considering various design constrains, such as power, area, and wirelength. For large systems, we also propose an efficient approach for obtaining competitive solutions with significant less computation time compared to the exhaustive approach. The accuracy of our analytical model is validated via SystemC simulation using several synthetic applications and an industrial SoC design.
UR - http://www.scopus.com/inward/record.url?scp=84857230452&partnerID=8YFLogxK
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U2 - 10.1109/SLIP.2011.6135433
DO - 10.1109/SLIP.2011.6135433
M3 - Conference contribution
AN - SCOPUS:84857230452
SN - 9781457712401
T3 - International Workshop on System Level Interconnect Prediction, SLIP
BT - 2011 13th International Workshop on System Level Interconnect Prediction, SLIP 2011
T2 - 2011 13th International Workshop on System Level Interconnect Prediction, SLIP 2011
Y2 - 5 June 2011 through 5 June 2011
ER -