Synthetic neural chip

R. O. Grondin; L. A. Akers; M. Walker; J. C. Wang; S. C. Chang; D. K. Ferry

Synthetic neural chip

R. O. Grondin, L. A. Akers, M. Walker, J. C. Wang, S. C. Chang, D. K. Ferry

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A compact synthetic neural cell that is compatible with CMOS technology is described. Some issues related to its applications are discussed. Particular emphasis is placed on training algorithms and connectivity. The chip architecture is presented along with the layout of a neural cell.

Original language	English (US)
Title of host publication	Conference Record - Asilomar Conference on Circuits, Systems & Computers
Editors	Ray R. Chen
Publisher	Publ by Maple Press, Inc
Pages	640-644
Number of pages	5
Volume	2
State	Published - 1988
Event	v 1 (of 2) - Pacific Grove, CA, USA Duration: Oct 31 1988 → Nov 2 1988

Other

Other	v 1 (of 2)
City	Pacific Grove, CA, USA
Period	10/31/88 → 11/2/88

ASJC Scopus subject areas

General Engineering

Cite this

@inproceedings{e0689f1529c249949b4e64c6b583f552,

title = "Synthetic neural chip",

abstract = "A compact synthetic neural cell that is compatible with CMOS technology is described. Some issues related to its applications are discussed. Particular emphasis is placed on training algorithms and connectivity. The chip architecture is presented along with the layout of a neural cell.",

author = "Grondin, {R. O.} and Akers, {L. A.} and M. Walker and Wang, {J. C.} and Chang, {S. C.} and Ferry, {D. K.}",

year = "1988",

language = "English (US)",

volume = "2",

pages = "640--644",

editor = "Chen, {Ray R.}",

booktitle = "Conference Record - Asilomar Conference on Circuits, Systems & Computers",

publisher = "Publ by Maple Press, Inc",

note = "v 1 (of 2) ; Conference date: 31-10-1988 Through 02-11-1988",

}

TY - GEN

T1 - Synthetic neural chip

AU - Grondin, R. O.

AU - Akers, L. A.

AU - Walker, M.

AU - Wang, J. C.

AU - Chang, S. C.

AU - Ferry, D. K.

PY - 1988

Y1 - 1988

N2 - A compact synthetic neural cell that is compatible with CMOS technology is described. Some issues related to its applications are discussed. Particular emphasis is placed on training algorithms and connectivity. The chip architecture is presented along with the layout of a neural cell.

AB - A compact synthetic neural cell that is compatible with CMOS technology is described. Some issues related to its applications are discussed. Particular emphasis is placed on training algorithms and connectivity. The chip architecture is presented along with the layout of a neural cell.

UR - http://www.scopus.com/inward/record.url?scp=0024186827&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024186827&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0024186827

VL - 2

SP - 640

EP - 644

BT - Conference Record - Asilomar Conference on Circuits, Systems & Computers

A2 - Chen, Ray R.

PB - Publ by Maple Press, Inc

T2 - v 1 (of 2)

Y2 - 31 October 1988 through 2 November 1988

ER -

Synthetic neural chip

Abstract

Other

ASJC Scopus subject areas

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Cite this