Synthetic neural chip

R. O. Grondin, L. A. Akers, M. Walker, J. C. Wang, S. C. Chang, D. K. Ferry

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A compact synthetic neural cell that is compatible with CMOS technology is described. Some issues related to its applications are discussed. Particular emphasis is placed on training algorithms and connectivity. The chip architecture is presented along with the layout of a neural cell.

Original languageEnglish (US)
Title of host publicationConference Record - Asilomar Conference on Circuits, Systems & Computers
EditorsRay R. Chen
PublisherPubl by Maple Press, Inc
Pages640-644
Number of pages5
Volume2
StatePublished - 1988
Eventv 1 (of 2) - Pacific Grove, CA, USA
Duration: Oct 31 1988Nov 2 1988

Other

Otherv 1 (of 2)
CityPacific Grove, CA, USA
Period10/31/8811/2/88

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Grondin, R. O., Akers, L. A., Walker, M., Wang, J. C., Chang, S. C., & Ferry, D. K. (1988). Synthetic neural chip. In R. R. Chen (Ed.), Conference Record - Asilomar Conference on Circuits, Systems & Computers (Vol. 2, pp. 640-644). Publ by Maple Press, Inc.