We investigate a promising coding scheme over channels impaired by insertion, deletion, and substitution errors, i.e., interleaved concatenation of an outer low-density parity-check (LDPC) code with error-correction capabilities and an inner marker code for synchronization purposes. To limit the decoding latency, we start with a single-pass decoding algorithm, that is, marker code-based synchronization is performed only once per received packet and iterative decoding with information exchange between the inner decoder and outer decoder is not allowed. Through numerical evaluations, we first find the marker code structures which offer the ultimate achievable rate when standard bit-level synchronization is performed. Then, to exploit the correlations in the likelihoods corresponding to different transmitted bits, we introduce a novel symbol-level synchronization algorithm that works on groups of consecutive bits, and show how it improves the achievable rate along with the error rate performance by capturing part of the rate loss due to interleaving. When decoding latency is not an issue and multiple-pass decoding is performed, we utilize extrinsic information transfer (EXIT) charts to analyze the convergence behavior of the receiver, which leads to design of outer LDPC codes with good degree distributions. Finally, design examples are provided along with simulation results which confirm the advantage of the newly designed codes over the ones optimized for the standard additive white Gaussian noise (AWGN) channels, especially for channels with severe synchronization problems.
- Insertion/deletion channel
- LDPC code design
- marker codes
ASJC Scopus subject areas
- Electrical and Electronic Engineering