Abstract
We investigate a promising coding scheme over channels impaired by insertion, deletion, and substitution errors, i.e., interleaved concatenation of an outer low-density parity-check (LDPC) code with error-correction capabilities and an inner marker code for synchronization purposes. To limit the decoding latency, we start with a single-pass decoding algorithm, that is, marker code-based synchronization is performed only once per received packet and iterative decoding with information exchange between the inner decoder and outer decoder is not allowed. Through numerical evaluations, we first find the marker code structures which offer the ultimate achievable rate when standard bit-level synchronization is performed. Then, to exploit the correlations in the likelihoods corresponding to different transmitted bits, we introduce a novel symbol-level synchronization algorithm that works on groups of consecutive bits, and show how it improves the achievable rate along with the error rate performance by capturing part of the rate loss due to interleaving. When decoding latency is not an issue and multiple-pass decoding is performed, we utilize extrinsic information transfer (EXIT) charts to analyze the convergence behavior of the receiver, which leads to design of outer LDPC codes with good degree distributions. Finally, design examples are provided along with simulation results which confirm the advantage of the newly designed codes over the ones optimized for the standard additive white Gaussian noise (AWGN) channels, especially for channels with severe synchronization problems.
| Original language | English (US) |
|---|---|
| Article number | 5733455 |
| Pages (from-to) | 1287-1297 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Communications |
| Volume | 59 |
| Issue number | 5 |
| DOIs | |
| State | Published - May 2011 |
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Keywords
- Insertion/deletion channel
- LDPC code design
- marker codes
- synchronization
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
Symbol-level synchronization and LDPC code design for insertion/deletion channels. / Wang, Feng; Fertonani, Dario; Duman, Tolga M.
In: IEEE Transactions on Communications, Vol. 59, No. 5, 5733455, 05.2011, p. 1287-1297.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Symbol-level synchronization and LDPC code design for insertion/deletion channels
AU - Wang, Feng
AU - Fertonani, Dario
AU - Duman, Tolga M.
PY - 2011/5
Y1 - 2011/5
N2 - We investigate a promising coding scheme over channels impaired by insertion, deletion, and substitution errors, i.e., interleaved concatenation of an outer low-density parity-check (LDPC) code with error-correction capabilities and an inner marker code for synchronization purposes. To limit the decoding latency, we start with a single-pass decoding algorithm, that is, marker code-based synchronization is performed only once per received packet and iterative decoding with information exchange between the inner decoder and outer decoder is not allowed. Through numerical evaluations, we first find the marker code structures which offer the ultimate achievable rate when standard bit-level synchronization is performed. Then, to exploit the correlations in the likelihoods corresponding to different transmitted bits, we introduce a novel symbol-level synchronization algorithm that works on groups of consecutive bits, and show how it improves the achievable rate along with the error rate performance by capturing part of the rate loss due to interleaving. When decoding latency is not an issue and multiple-pass decoding is performed, we utilize extrinsic information transfer (EXIT) charts to analyze the convergence behavior of the receiver, which leads to design of outer LDPC codes with good degree distributions. Finally, design examples are provided along with simulation results which confirm the advantage of the newly designed codes over the ones optimized for the standard additive white Gaussian noise (AWGN) channels, especially for channels with severe synchronization problems.
AB - We investigate a promising coding scheme over channels impaired by insertion, deletion, and substitution errors, i.e., interleaved concatenation of an outer low-density parity-check (LDPC) code with error-correction capabilities and an inner marker code for synchronization purposes. To limit the decoding latency, we start with a single-pass decoding algorithm, that is, marker code-based synchronization is performed only once per received packet and iterative decoding with information exchange between the inner decoder and outer decoder is not allowed. Through numerical evaluations, we first find the marker code structures which offer the ultimate achievable rate when standard bit-level synchronization is performed. Then, to exploit the correlations in the likelihoods corresponding to different transmitted bits, we introduce a novel symbol-level synchronization algorithm that works on groups of consecutive bits, and show how it improves the achievable rate along with the error rate performance by capturing part of the rate loss due to interleaving. When decoding latency is not an issue and multiple-pass decoding is performed, we utilize extrinsic information transfer (EXIT) charts to analyze the convergence behavior of the receiver, which leads to design of outer LDPC codes with good degree distributions. Finally, design examples are provided along with simulation results which confirm the advantage of the newly designed codes over the ones optimized for the standard additive white Gaussian noise (AWGN) channels, especially for channels with severe synchronization problems.
KW - Insertion/deletion channel
KW - LDPC code design
KW - marker codes
KW - synchronization
UR - http://www.scopus.com/inward/record.url?scp=79956260270&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79956260270&partnerID=8YFLogxK
U2 - 10.1109/TCOMM.2011.030411.100546
DO - 10.1109/TCOMM.2011.030411.100546
M3 - Article
VL - 59
SP - 1287
EP - 1297
JO - IEEE Transactions on Communications
JF - IEEE Transactions on Communications
SN - 0090-6778
IS - 5
M1 - 5733455
ER -