Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis

Yu Cao, Xiao Dong Yang, Xuejue Huang, Dennis Sylvester

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Timing uncertainty caused by inductive and capacitive coupling is one of the major bottlenecks in timing analysis. In this paper, we propose an effective loop RLC modeling technique to efficiently decouple lines with both inductive and capacitive coupling. We generalize the RLC decoupling problem based on transmission line theory and a switch-factor, which is the voltage ratio between two nets. This switch-factor is also known as the Miller factor and is widely used to model capacitive coupling. The proposed modeling technique can be directly applied to partial RLC netlists extracted using existing parasitic extraction tools without advance knowledge of the return path. The new model accurately captures the impact of neighboring switching activity when it significantly affects the size of current return loop. As demonstrated in our experiments, the new model accurately predicts both upper and lower delay bounds as a function of neighboring switching patterns. Therefore, this approach can be easily implemented into existing timing analysis flows such as max-timing and min-timing analysis. Finally, we apply the new modeling approach to a range of activities across the design process including timing optimization, static timing analysis, high frequency clock design, and data-bus wire planning.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Pages848-853
Number of pages6
StatePublished - 2003
Externally publishedYes
EventIEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers - San Jose, CA, United States
Duration: Nov 9 2003Nov 13 2003

Other

OtherIEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers
CountryUnited States
CitySan Jose, CA
Period11/9/0311/13/03

Keywords

  • Clock
  • Current return loop
  • Data-bus
  • Loop inductance
  • RLC model
  • Slew rate
  • Static timing analysis
  • Switch-factor

ASJC Scopus subject areas

  • Software

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  • Cite this

    Cao, Y., Yang, X. D., Huang, X., & Sylvester, D. (2003). Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (pp. 848-853)