STT-MRAM Design Technology Co-optimization for Hardware Neural Networks

Nuo Xu, Yang Lu, Weiyi Qi, Zhengping Jiang, Xiaochen Peng, Fan Chen, Jing Wang, Woosung Choi, Shimeng Yu, Dae Sin Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

The potential of embedded STT-MRAM technology for designing large-scale multiply-and-accumulation (MAC) array circuits are evaluated by comprehensive and holistic design-technology co-optimizations. After careful calibrations with experimental data, post-layout circuit simulations together with GPU-enabled massively parallel Monte Carlo evaluations are conducted to guarantee the designs at rare failure rates. With all critical device and design non-idealities included, architectural emulations are performed to examine the hardware neural network (HNN)'s accuracies and estimate system-level power, performance and area specs. Results indicate the amount of process variation, parasites and error levels to control in order to achieve a feasible solution for STT-MRAM based HNNs.

Original languageEnglish (US)
Title of host publication2018 IEEE International Electron Devices Meeting, IEDM 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages15.3.1-15.3.4
ISBN (Electronic)9781728119878
DOIs
StatePublished - Jan 16 2019
Event64th Annual IEEE International Electron Devices Meeting, IEDM 2018 - San Francisco, United States
Duration: Dec 1 2018Dec 5 2018

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2018-December
ISSN (Print)0163-1918

Conference

Conference64th Annual IEEE International Electron Devices Meeting, IEDM 2018
CountryUnited States
CitySan Francisco
Period12/1/1812/5/18

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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  • Cite this

    Xu, N., Lu, Y., Qi, W., Jiang, Z., Peng, X., Chen, F., Wang, J., Choi, W., Yu, S., & Kim, D. S. (2019). STT-MRAM Design Technology Co-optimization for Hardware Neural Networks. In 2018 IEEE International Electron Devices Meeting, IEDM 2018 (pp. 15.3.1-15.3.4). [8614560] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2018.8614560