@inproceedings{b7755f939caa4c7daa1cdc8323714cdd,
title = "STT-MRAM Design Technology Co-optimization for Hardware Neural Networks",
abstract = "The potential of embedded STT-MRAM technology for designing large-scale multiply-and-accumulation (MAC) array circuits are evaluated by comprehensive and holistic design-technology co-optimizations. After careful calibrations with experimental data, post-layout circuit simulations together with GPU-enabled massively parallel Monte Carlo evaluations are conducted to guarantee the designs at rare failure rates. With all critical device and design non-idealities included, architectural emulations are performed to examine the hardware neural network (HNN)'s accuracies and estimate system-level power, performance and area specs. Results indicate the amount of process variation, parasites and error levels to control in order to achieve a feasible solution for STT-MRAM based HNNs.",
author = "Nuo Xu and Yang Lu and Weiyi Qi and Zhengping Jiang and Xiaochen Peng and Fan Chen and Jing Wang and Woosung Choi and Shimeng Yu and Kim, {Dae Sin}",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 64th Annual IEEE International Electron Devices Meeting, IEDM 2018 ; Conference date: 01-12-2018 Through 05-12-2018",
year = "2019",
month = jan,
day = "16",
doi = "10.1109/IEDM.2018.8614560",
language = "English (US)",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "15.3.1--15.3.4",
booktitle = "2018 IEEE International Electron Devices Meeting, IEDM 2018",
}