Statistical waveform and current source based standard cell models for accurate timing analysis

Amit Goel, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

Abstract

Increasing variability in the manufacturing process and growing complexity of the integrated circuits has given rise to many design and verification challenges. Statistical analysis of circuits and current source based gate delay models have started to replace the conventional static timing analysis which uses lookup tables for gate delays. In this paper we develop a statistical current source based gate model. We use accurate analytical models for representing the parameters of the gate model as functions of process parameters. Using the proposed statistical gate model, the gate output signal is generated and modeled as process dependent variational waveform. We present a compact model for representation of the variational signal waveform. The proposed waveform model can accurately generate the signal waveform at any process corner for accurate timing analysis. We generated the prosed model for gates of a 90nm industry library and validated with SPICE simulations. Our model for logic gates and variational waveforms showed very good correlation with SPICE. The maximum error across all validation experiments was close to 3%.

Original languageEnglish (US)
Title of host publicationProceedings of the 45th Design Automation Conference, DAC
Pages227-230
Number of pages4
DOIs
StatePublished - Sep 17 2008
Event45th Design Automation Conference, DAC - Anaheim, CA, United States
Duration: Jun 8 2008Jun 13 2008

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other45th Design Automation Conference, DAC
CountryUnited States
CityAnaheim, CA
Period6/8/086/13/08

Keywords

  • Process variations
  • Statistical waveform models
  • Timing analysis

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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