Abstract
Increasing numbers of analog components in today's systems necessitate system level test composition methods that utilize on-chip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance analysis methodology is undertaken by comparing our results with detailed SPICE Monte-Carlo simulation data on several combinations of analog modules. The results of our experiments confirm the high accuracy and efficiency of the proposed tolerance analysis methodology.
Original language | English (US) |
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Pages (from-to) | 173-182 |
Number of pages | 10 |
Journal | Journal of Electronic Testing: Theory and Applications (JETTA) |
Volume | 19 |
Issue number | 2 |
DOIs | |
State | Published - Apr 2003 |
Externally published | Yes |
Keywords
- Analog test
- Statistical analysis
- Test signal propagation
- Tolerance analysis
ASJC Scopus subject areas
- Electrical and Electronic Engineering