Abstract
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis which uses statistical bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical timing analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay, we can determine the quality of the bounds. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings -Design, Automation and Test in Europe, DATE |
| Pages | 62-67 |
| Number of pages | 6 |
| DOIs | |
| State | Published - 2003 |
| Event | Design, Automation and Test in Europe Conference and Exhibition, DATE 2003 - Munich, Germany Duration: Mar 3 2003 → Mar 7 2003 |
Other
| Other | Design, Automation and Test in Europe Conference and Exhibition, DATE 2003 |
|---|---|
| Country | Germany |
| City | Munich |
| Period | 3/3/03 → 3/7/03 |
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ASJC Scopus subject areas
- Engineering(all)
Cite this
Statistical timing analysis using bounds. / Agarwal, Aseem; Blaauw, David; Zolotov, Vladimir; Vrudhula, Sarma.
Proceedings -Design, Automation and Test in Europe, DATE. 2003. p. 62-67 1253588.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Statistical timing analysis using bounds
AU - Agarwal, Aseem
AU - Blaauw, David
AU - Zolotov, Vladimir
AU - Vrudhula, Sarma
PY - 2003
Y1 - 2003
N2 - The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis which uses statistical bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical timing analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay, we can determine the quality of the bounds. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error.
AB - The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper, we propose a new approach to statistical timing analysis which uses statistical bounds. First, we provide a formal definition of the statistical delay of a circuit and derive a statistical timing analysis method from this definition. Since this method for finding the exact statistical delay has exponential run time complexity with circuit size, we also propose a new method for computing statistical bounds which has linear run time complexity. We prove the correctness of the proposed bounds. Since we provide both a lower and upper bound on the true statistical delay, we can determine the quality of the bounds. The proposed methods were implemented and tested on benchmark circuits. The results demonstrate that the proposed bounds have only a small error.
UR - http://www.scopus.com/inward/record.url?scp=18144420677&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=18144420677&partnerID=8YFLogxK
U2 - 10.1109/DATE.2003.1253588
DO - 10.1109/DATE.2003.1253588
M3 - Conference contribution
AN - SCOPUS:18144420677
SP - 62
EP - 67
BT - Proceedings -Design, Automation and Test in Europe, DATE
ER -