Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness

Yun Ye, Frank Liu, Sani Nassif, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

39 Citations (Scopus)

Abstract

The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive computationally for statistical circuit design. In this work, we develop an efficient SPICE simulation method and statistical transistor model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth; and (c) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations. The proposed SPICE simulation method is fully validated against atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, to help shed light on the challenges of future robust circuit design.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages900-905
Number of pages6
DOIs
StatePublished - 2008
Event45th Design Automation Conference, DAC - Anaheim, CA, United States
Duration: Jun 8 2008Jun 13 2008

Other

Other45th Design Automation Conference, DAC
CountryUnited States
CityAnaheim, CA
Period6/8/086/13/08

Fingerprint

Surface roughness
Doping (additives)
SPICE
Lithography
Transistors
Networks (circuits)
Threshold voltage
Leakage currents
Etching
Wavelength
Geometry

Keywords

  • Atomistic simulations
  • Line-edge roughness
  • Non-rectangular gate
  • Predictive modeling
  • Random dopant fluctuations
  • SPICE simulation
  • Threshold variation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Ye, Y., Liu, F., Nassif, S., & Cao, Y. (2008). Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. In Proceedings - Design Automation Conference (pp. 900-905). [4555948] https://doi.org/10.1109/DAC.2008.4555948

Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. / Ye, Yun; Liu, Frank; Nassif, Sani; Cao, Yu.

Proceedings - Design Automation Conference. 2008. p. 900-905 4555948.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ye, Y, Liu, F, Nassif, S & Cao, Y 2008, Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. in Proceedings - Design Automation Conference., 4555948, pp. 900-905, 45th Design Automation Conference, DAC, Anaheim, CA, United States, 6/8/08. https://doi.org/10.1109/DAC.2008.4555948
Ye, Yun ; Liu, Frank ; Nassif, Sani ; Cao, Yu. / Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. Proceedings - Design Automation Conference. 2008. pp. 900-905
@inproceedings{dfd3204db9874c4ea86f0df0b5d11dae,
title = "Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness",
abstract = "The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive computationally for statistical circuit design. In this work, we develop an efficient SPICE simulation method and statistical transistor model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth; and (c) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations. The proposed SPICE simulation method is fully validated against atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, to help shed light on the challenges of future robust circuit design.",
keywords = "Atomistic simulations, Line-edge roughness, Non-rectangular gate, Predictive modeling, Random dopant fluctuations, SPICE simulation, Threshold variation",
author = "Yun Ye and Frank Liu and Sani Nassif and Yu Cao",
year = "2008",
doi = "10.1109/DAC.2008.4555948",
language = "English (US)",
isbn = "9781605581156",
pages = "900--905",
booktitle = "Proceedings - Design Automation Conference",

}

TY - GEN

T1 - Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness

AU - Ye, Yun

AU - Liu, Frank

AU - Nassif, Sani

AU - Cao, Yu

PY - 2008

Y1 - 2008

N2 - The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive computationally for statistical circuit design. In this work, we develop an efficient SPICE simulation method and statistical transistor model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth; and (c) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations. The proposed SPICE simulation method is fully validated against atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, to help shed light on the challenges of future robust circuit design.

AB - The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive computationally for statistical circuit design. In this work, we develop an efficient SPICE simulation method and statistical transistor model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of Vth from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to Vth; and (c) propose a compact model of Vth variation that is scalable with gate size and the amount of dopant and gate length fluctuations. The proposed SPICE simulation method is fully validated against atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of Vth variation at advanced technology nodes, to help shed light on the challenges of future robust circuit design.

KW - Atomistic simulations

KW - Line-edge roughness

KW - Non-rectangular gate

KW - Predictive modeling

KW - Random dopant fluctuations

KW - SPICE simulation

KW - Threshold variation

UR - http://www.scopus.com/inward/record.url?scp=51549098014&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=51549098014&partnerID=8YFLogxK

U2 - 10.1109/DAC.2008.4555948

DO - 10.1109/DAC.2008.4555948

M3 - Conference contribution

AN - SCOPUS:51549098014

SN - 9781605581156

SP - 900

EP - 905

BT - Proceedings - Design Automation Conference

ER -