A comprehensive assessment methodology for the design and optimization of cross-point resistive random access memory (RRAM) arrays is developed based on a simulation platform implementing an RRAM SPICE model with intrinsic variation effects. A statistical assessment of write/read functionality and circuit reliability is performed via quantifying the impact of array-level variations on RRAM memory circuits. Operation reliability including write failure probability and write disturb effect is quantified, with a strategy of choosing bias schemes and a Vdd design tradeoff presented. Circuit/device co-design guidelines and requirements are further extracted based on the assessment of a series of figure-of-merits such as energy-delay product, disturb immunity, and interconnect scaling effect. Finally, an optimized cross-point array configuration is designed to boost circuit performance. The developed assessment flow will pave the way towards robust circuit/device co-design.