Statistical aging under dynamic voltage scaling: A logarithmic model approach

Jyothi B. Velamala, Ketul Sutaria, Hirofumi Shimizu, Hiromitsu Awano, Takashi Sato, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

Aging mechanisms, such as Negative Bias Temperature Instability (NBTI), limit the lifetime of CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction in real circuit operation. To overcome these barriers, this work (1) proposes a logarithmic model (log(t)) that is derived from the trapping/de-trapping assumptions; (2) practically explains the aging statistics and the non-monotonic behavior under dynamic voltage scaling (DVS); and (3) comprehensively validates the new model with 65nm silicon data. Compared to previous models, the new result captures the essential role of the recovery phase under DVS, reducing unnecessary guard-banding in reliability protection.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012
DOIs
StatePublished - Nov 26 2012
Event34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA, United States
Duration: Sep 9 2012Sep 12 2012

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other34th Annual Custom Integrated Circuits Conference, CICC 2012
CountryUnited States
CitySan Jose, CA
Period9/9/129/12/12

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Statistical aging under dynamic voltage scaling: A logarithmic model approach'. Together they form a unique fingerprint.

  • Cite this

    Velamala, J. B., Sutaria, K., Shimizu, H., Awano, H., Sato, T., & Cao, Y. (2012). Statistical aging under dynamic voltage scaling: A logarithmic model approach. In Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012 [6330572] (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2012.6330572