Statistical aging under dynamic voltage scaling: A logarithmic model approach

Jyothi B. Velamala; Ketul Sutaria; Hirofumi Shimizu; Hiromitsu Awano; Takashi Sato; Yu Cao

doi:10.1109/CICC.2012.6330572

Statistical aging under dynamic voltage scaling: A logarithmic model approach

Jyothi B. Velamala, Ketul Sutaria, Hirofumi Shimizu, Hiromitsu Awano, Takashi Sato, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Scopus citations

Abstract

Aging mechanisms, such as Negative Bias Temperature Instability (NBTI), limit the lifetime of CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tⁿ). Such discrepancies further pose the challenge on long-term reliability prediction in real circuit operation. To overcome these barriers, this work (1) proposes a logarithmic model (log(t)) that is derived from the trapping/de-trapping assumptions; (2) practically explains the aging statistics and the non-monotonic behavior under dynamic voltage scaling (DVS); and (3) comprehensively validates the new model with 65nm silicon data. Compared to previous models, the new result captures the essential role of the recovery phase under DVS, reducing unnecessary guard-banding in reliability protection.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012
DOIs	https://doi.org/10.1109/CICC.2012.6330572
State	Published - 2012
Event	34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA, United States Duration: Sep 9 2012 → Sep 12 2012

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	34th Annual Custom Integrated Circuits Conference, CICC 2012
Country/Territory	United States
City	San Jose, CA
Period	9/9/12 → 9/12/12

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/CICC.2012.6330572

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Statistical aging under dynamic voltage scaling: A logarithmic model approach. / Velamala, Jyothi B.; Sutaria, Ketul; Shimizu, Hirofumi et al.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012. 2012. 6330572 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Velamala, JB, Sutaria, K, Shimizu, H, Awano, H, Sato, T & Cao, Y 2012, Statistical aging under dynamic voltage scaling: A logarithmic model approach. in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012., 6330572, Proceedings of the Custom Integrated Circuits Conference, 34th Annual Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, United States, 9/9/12. https://doi.org/10.1109/CICC.2012.6330572

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abstract = "Aging mechanisms, such as Negative Bias Temperature Instability (NBTI), limit the lifetime of CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction in real circuit operation. To overcome these barriers, this work (1) proposes a logarithmic model (log(t)) that is derived from the trapping/de-trapping assumptions; (2) practically explains the aging statistics and the non-monotonic behavior under dynamic voltage scaling (DVS); and (3) comprehensively validates the new model with 65nm silicon data. Compared to previous models, the new result captures the essential role of the recovery phase under DVS, reducing unnecessary guard-banding in reliability protection.",

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AU - Velamala, Jyothi B.

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AU - Awano, Hiromitsu

AU - Sato, Takashi

AU - Cao, Yu

PY - 2012

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AB - Aging mechanisms, such as Negative Bias Temperature Instability (NBTI), limit the lifetime of CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction in real circuit operation. To overcome these barriers, this work (1) proposes a logarithmic model (log(t)) that is derived from the trapping/de-trapping assumptions; (2) practically explains the aging statistics and the non-monotonic behavior under dynamic voltage scaling (DVS); and (3) comprehensively validates the new model with 65nm silicon data. Compared to previous models, the new result captures the essential role of the recovery phase under DVS, reducing unnecessary guard-banding in reliability protection.

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Statistical aging under dynamic voltage scaling: A logarithmic model approach

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