Static power optimization of deep submicron CMOS circuits for dual V T technology

Research output: Chapter in Book/Report/Conference proceedingConference contribution

72 Scopus citations

Abstract

In this paper we address the problem of delay constrained minimization of leakage power of CMOS digital circuits for dual V T technology. A novel and efficient heuristic algorithm based on circuit graph enumeration is proposed. The experimental results on the MCNC91 benchmark circuits show that up to an order of magnitude power reduction can be achieved without any increase in delay.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
EditorsH. Yasuura, J. White
PublisherIEEE Comp Soc
Pages490-494
Number of pages5
StatePublished - 1998
Externally publishedYes
EventProceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD - San Jose, CA, USA
Duration: Nov 8 1998Nov 12 1998

Other

OtherProceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
CitySan Jose, CA, USA
Period11/8/9811/12/98

ASJC Scopus subject areas

  • Software

Fingerprint Dive into the research topics of 'Static power optimization of deep submicron CMOS circuits for dual V <sub>T</sub> technology'. Together they form a unique fingerprint.

Cite this