Static power optimization of deep submicron CMOS circuits for dual V
            T technology

Qi Wang; Sarma B K Vrudhula

Static power optimization of deep submicron CMOS circuits for dual V _T technology

Qi Wang, Sarma B K Vrudhula

Computing and Augmented Intelligence, School of (IAFSE-SCAI)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

72 Scopus citations

Abstract

In this paper we address the problem of delay constrained minimization of leakage power of CMOS digital circuits for dual V _T technology. A novel and efficient heuristic algorithm based on circuit graph enumeration is proposed. The experimental results on the MCNC91 benchmark circuits show that up to an order of magnitude power reduction can be achieved without any increase in delay.

Original language	English (US)
Title of host publication	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Editors	H. Yasuura, J. White
Publisher	IEEE Comp Soc
Pages	490-494
Number of pages	5
State	Published - 1998
Event	Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD - San Jose, CA, USA Duration: Nov 8 1998 → Nov 12 1998

Other

Other	Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
City	San Jose, CA, USA
Period	11/8/98 → 11/12/98

ASJC Scopus subject areas

Software

Cite this

Static power optimization of deep submicron CMOS circuits for dual V _T technology . / Wang, Qi; Vrudhula, Sarma B K.
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. ed. / H. Yasuura; J. White. IEEE Comp Soc, 1998. p. 490-494.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, Q & Vrudhula, SBK 1998, Static power optimization of deep submicron CMOS circuits for dual V _T technology in H Yasuura & J White (eds), IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. IEEE Comp Soc, pp. 490-494, Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD, San Jose, CA, USA, 11/8/98.

@inproceedings{6b29cf6b7fdf4d588e88b85883752220,

title = "Static power optimization of deep submicron CMOS circuits for dual V T technology ",

abstract = "In this paper we address the problem of delay constrained minimization of leakage power of CMOS digital circuits for dual V T technology. A novel and efficient heuristic algorithm based on circuit graph enumeration is proposed. The experimental results on the MCNC91 benchmark circuits show that up to an order of magnitude power reduction can be achieved without any increase in delay. ",

author = "Qi Wang and Vrudhula, {Sarma B K}",

year = "1998",

language = "English (US)",

pages = "490--494",

editor = "H. Yasuura and J. White",

booktitle = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers",

publisher = "IEEE Comp Soc",

note = "Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD ; Conference date: 08-11-1998 Through 12-11-1998",

}

TY - GEN

T1 - Static power optimization of deep submicron CMOS circuits for dual V T technology

AU - Wang, Qi

AU - Vrudhula, Sarma B K

PY - 1998

Y1 - 1998

N2 - In this paper we address the problem of delay constrained minimization of leakage power of CMOS digital circuits for dual V T technology. A novel and efficient heuristic algorithm based on circuit graph enumeration is proposed. The experimental results on the MCNC91 benchmark circuits show that up to an order of magnitude power reduction can be achieved without any increase in delay.

AB - In this paper we address the problem of delay constrained minimization of leakage power of CMOS digital circuits for dual V T technology. A novel and efficient heuristic algorithm based on circuit graph enumeration is proposed. The experimental results on the MCNC91 benchmark circuits show that up to an order of magnitude power reduction can be achieved without any increase in delay.

UR - http://www.scopus.com/inward/record.url?scp=0032319165&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032319165&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0032319165

SP - 490

EP - 494

BT - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

A2 - Yasuura, H.

A2 - White, J.

PB - IEEE Comp Soc

T2 - Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD

Y2 - 8 November 1998 through 12 November 1998

ER -

Static power optimization of deep submicron CMOS circuits for dual V _T technology

Abstract

Other

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this