Static analysis of processor stall cycle aggregation

Jongeun Lee, Aviral Shrivastava

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the processor is switched to low-power mode in it. We extend the previous proposed approach in two dimensions, i) We develop static analysis for the PICA technique and present optimum parameters for five common types of loops based on steady-state analysis, ii) We show that software only control is unable to guarantee its correctness in a varying runtime environment, potentially causing deadlocks. We enhance the robustness of PICA with minimal hardware extension, ensuring correct execution for any loops and parameters, which greatly facilitates exploration based parameter optimization. The combined use of our static analysis and exploration based fine-tuning makes the PICA technique applicable, to any memory-bound loop, with energy reduction. We validate our analytical models against simulation based optimization and also show through our experiments on embedded application benchmarks, that our technique can be applied to a wide range of loops with average 20% energy reductions compared to executions without PICA.

Original languageEnglish (US)
Title of host publicationEmbedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008
Pages25-30
Number of pages6
DOIs
StatePublished - Dec 1 2008
EventEmbedded Systems Week 2008 - 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008 - Atlanta, GA, United States
Duration: Oct 19 2008Oct 24 2008

Publication series

NameEmbedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

Other

OtherEmbedded Systems Week 2008 - 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008
CountryUnited States
CityAtlanta, GA
Period10/19/0810/24/08

Keywords

  • Code transformation
  • Embedded systems
  • Low power
  • Memory bound loops
  • Processor free time
  • Stall cycle aggregation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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  • Cite this

    Lee, J., & Shrivastava, A. (2008). Static analysis of processor stall cycle aggregation. In Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008 (pp. 25-30). (Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008). https://doi.org/10.1145/1450135.1450143