Standby supply voltage minimization for deep sub-micron SRAM

Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan Rabaey

Research output: Contribution to journalConference articlepeer-review

46 Scopus citations


Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. The DRV model is verified using simulations as well as measurements from a 4 KB SRAM chip in a 0.13 μm technology. Due to a large on-chip variation, DRV of the 4 KB SRAM module ranges between 60 and 390 mV. Measurements taken at 100 mV above the worst-case DRV show that reducing the SRAM standby VDD to a safe level of 490 mV saves 85% leakage power. Further savings can be achieved by applying DRV-aware SRAM optimization techniques, which are discussed at the end of this paper.

Original languageEnglish (US)
Pages (from-to)789-800
Number of pages12
JournalMicroelectronics Journal
Issue number9
StatePublished - Sep 2005
Externally publishedYes


  • DRV
  • Data retention
  • Leakage suppression
  • SRAM
  • State preservation
  • Variation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering


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