Standard cell library and automated design flow for circuits on flexible substrates

Shrinivas Gopalan Uppili; David Allee; Sameer M. Venugopal; Lawrence T. Clark; Rahul Shringarpure

doi:10.1109/FEDC.2009.5069270

Standard cell library and automated design flow for circuits on flexible substrates

Shrinivas Gopalan Uppili, David Allee, Sameer M. Venugopal, Lawrence T. Clark, Rahul Shringarpure

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

A-Si:H TFTs are traditionally used in backplane arrays for active matrix displays and occasionally in row or column drive electronics with current efforts focusing on flexible displays and drivers. This paper extends flexible electronics to complex digital circuitry by designing a standard cell library for a-Si:H TFTs on flexible stainless steel and plastic substrates. The standard cell library enables layout automation with a standard cell place and route tool, significantly speeding the layout of a-Si:H digital circuits on the backplane to enhance display functionality. Since only n-channel transistors are available, the gates are designed with a bootstrap pull-up network to ensure good output voltage swings. The library developed consists of 7 gates: 5 combinational gates (Inverter, NAND2, NOR2, NOR3, and MUX2) and 2 sequential gates (latch and 'D' flip-flop). Test structures have been fabricated to experimentally characterize the delay vs. fanout of the standard cells. Automatic extraction of electrical interconnections from layout, enabling layout versus schematic (LVS) has also incorporated into the existing tool suite for bottom gate a-Si:H TFTs. A 3bit counter was designed, fabricated and tested to demonstrate the standard cell library is described.

Original language	English (US)
Title of host publication	2009 Flexible Electronics and Displays Conference and Exhibition, FLEX 2009
DOIs	https://doi.org/10.1109/FEDC.2009.5069270
State	Published - 2009
Event	Flexible Electronics and Displays Conference and Exhibition, FLEX 2009 - Duration: Feb 2 2009 → Feb 2 2009

Other

Other	Flexible Electronics and Displays Conference and Exhibition, FLEX 2009
Period	2/2/09 → 2/2/09

Keywords

a-Si:H TFT
Automatic place and route
Flexible electronics
Standard cell library
Threshold voltage degradation

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/FEDC.2009.5069270

Cite this

@inproceedings{55a9fdd5d91a4e57b6169432ff593785,

title = "Standard cell library and automated design flow for circuits on flexible substrates",

abstract = "A-Si:H TFTs are traditionally used in backplane arrays for active matrix displays and occasionally in row or column drive electronics with current efforts focusing on flexible displays and drivers. This paper extends flexible electronics to complex digital circuitry by designing a standard cell library for a-Si:H TFTs on flexible stainless steel and plastic substrates. The standard cell library enables layout automation with a standard cell place and route tool, significantly speeding the layout of a-Si:H digital circuits on the backplane to enhance display functionality. Since only n-channel transistors are available, the gates are designed with a bootstrap pull-up network to ensure good output voltage swings. The library developed consists of 7 gates: 5 combinational gates (Inverter, NAND2, NOR2, NOR3, and MUX2) and 2 sequential gates (latch and 'D' flip-flop). Test structures have been fabricated to experimentally characterize the delay vs. fanout of the standard cells. Automatic extraction of electrical interconnections from layout, enabling layout versus schematic (LVS) has also incorporated into the existing tool suite for bottom gate a-Si:H TFTs. A 3bit counter was designed, fabricated and tested to demonstrate the standard cell library is described.",

keywords = "a-Si:H TFT, Automatic place and route, Flexible electronics, Standard cell library, Threshold voltage degradation",

author = "Uppili, {Shrinivas Gopalan} and David Allee and Venugopal, {Sameer M.} and Clark, {Lawrence T.} and Rahul Shringarpure",

year = "2009",

doi = "10.1109/FEDC.2009.5069270",

language = "English (US)",

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AU - Allee, David

AU - Venugopal, Sameer M.

AU - Clark, Lawrence T.

AU - Shringarpure, Rahul

PY - 2009

Y1 - 2009

N2 - A-Si:H TFTs are traditionally used in backplane arrays for active matrix displays and occasionally in row or column drive electronics with current efforts focusing on flexible displays and drivers. This paper extends flexible electronics to complex digital circuitry by designing a standard cell library for a-Si:H TFTs on flexible stainless steel and plastic substrates. The standard cell library enables layout automation with a standard cell place and route tool, significantly speeding the layout of a-Si:H digital circuits on the backplane to enhance display functionality. Since only n-channel transistors are available, the gates are designed with a bootstrap pull-up network to ensure good output voltage swings. The library developed consists of 7 gates: 5 combinational gates (Inverter, NAND2, NOR2, NOR3, and MUX2) and 2 sequential gates (latch and 'D' flip-flop). Test structures have been fabricated to experimentally characterize the delay vs. fanout of the standard cells. Automatic extraction of electrical interconnections from layout, enabling layout versus schematic (LVS) has also incorporated into the existing tool suite for bottom gate a-Si:H TFTs. A 3bit counter was designed, fabricated and tested to demonstrate the standard cell library is described.

AB - A-Si:H TFTs are traditionally used in backplane arrays for active matrix displays and occasionally in row or column drive electronics with current efforts focusing on flexible displays and drivers. This paper extends flexible electronics to complex digital circuitry by designing a standard cell library for a-Si:H TFTs on flexible stainless steel and plastic substrates. The standard cell library enables layout automation with a standard cell place and route tool, significantly speeding the layout of a-Si:H digital circuits on the backplane to enhance display functionality. Since only n-channel transistors are available, the gates are designed with a bootstrap pull-up network to ensure good output voltage swings. The library developed consists of 7 gates: 5 combinational gates (Inverter, NAND2, NOR2, NOR3, and MUX2) and 2 sequential gates (latch and 'D' flip-flop). Test structures have been fabricated to experimentally characterize the delay vs. fanout of the standard cells. Automatic extraction of electrical interconnections from layout, enabling layout versus schematic (LVS) has also incorporated into the existing tool suite for bottom gate a-Si:H TFTs. A 3bit counter was designed, fabricated and tested to demonstrate the standard cell library is described.

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KW - Automatic place and route

KW - Flexible electronics

KW - Standard cell library

KW - Threshold voltage degradation

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Standard cell library and automated design flow for circuits on flexible substrates

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