Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the Data Retention Voltage (DRV), leakage power can be substantially reduced. This paper explores how low DRV can be in a standard low leakage SRAM module and analyzes how DRV is affected by parameters such as process variations, chip temperature, and transistor sizing. An analytical model for DRV as a function of process and design parameters is presented, and forms the base for further design space explorations. This model is verified using simulations as well as measurements from a 4KB SRAM chip in a 0.13μm technology. It is demonstrated that an SRAM cell state can be preserved at sub-300mV standby VDD, with more than 90% leakage power savings.