SRAM leakage suppression by minimizing standby supply voltage

Huifang Qin; Yu Cao; Dejan Markovic; Andrei Vladimirescu; Jan Rabaey

doi:10.1109/isqed.2004.1283650

SRAM leakage suppression by minimizing standby supply voltage

Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan Rabaey

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

175 Scopus citations

Abstract

Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the Data Retention Voltage (DRV), leakage power can be substantially reduced. This paper explores how low DRV can be in a standard low leakage SRAM module and analyzes how DRV is affected by parameters such as process variations, chip temperature, and transistor sizing. An analytical model for DRV as a function of process and design parameters is presented, and forms the base for further design space explorations. This model is verified using simulations as well as measurements from a 4KB SRAM chip in a 0.13μm technology. It is demonstrated that an SRAM cell state can be preserved at sub-300mV standby V_DD, with more than 90% leakage power savings.

Original language	English (US)
Title of host publication	Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004
Publisher	IEEE Computer Society
Pages	55-60
Number of pages	6
ISBN (Print)	0769520936, 9780769520933
DOIs	https://doi.org/10.1109/isqed.2004.1283650
State	Published - 2004
Externally published	Yes
Event	Proceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004 - San Jose, CA, United States Duration: Mar 22 2004 → Mar 24 2004

Publication series

Name	Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Conference

Conference	Proceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004
Country/Territory	United States
City	San Jose, CA
Period	3/22/04 → 3/24/04

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/isqed.2004.1283650

Cite this

Qin, H., Cao, Y., Markovic, D., Vladimirescu, A., & Rabaey, J. (2004). SRAM leakage suppression by minimizing standby supply voltage. In Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004 (pp. 55-60). (Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004). IEEE Computer Society. https://doi.org/10.1109/isqed.2004.1283650

SRAM leakage suppression by minimizing standby supply voltage. / Qin, Huifang; Cao, Yu; Markovic, Dejan et al.
Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004. IEEE Computer Society, 2004. p. 55-60 (Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Qin, H, Cao, Y, Markovic, D, Vladimirescu, A & Rabaey, J 2004, SRAM leakage suppression by minimizing standby supply voltage. in Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004. Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004, IEEE Computer Society, pp. 55-60, Proceedings - 5th International Symposium on Quality Electronic Design, ISQED 2004, San Jose, CA, United States, 3/22/04. https://doi.org/10.1109/isqed.2004.1283650

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abstract = "Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the Data Retention Voltage (DRV), leakage power can be substantially reduced. This paper explores how low DRV can be in a standard low leakage SRAM module and analyzes how DRV is affected by parameters such as process variations, chip temperature, and transistor sizing. An analytical model for DRV as a function of process and design parameters is presented, and forms the base for further design space explorations. This model is verified using simulations as well as measurements from a 4KB SRAM chip in a 0.13μm technology. It is demonstrated that an SRAM cell state can be preserved at sub-300mV standby VDD, with more than 90% leakage power savings.",

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AB - Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the Data Retention Voltage (DRV), leakage power can be substantially reduced. This paper explores how low DRV can be in a standard low leakage SRAM module and analyzes how DRV is affected by parameters such as process variations, chip temperature, and transistor sizing. An analytical model for DRV as a function of process and design parameters is presented, and forms the base for further design space explorations. This model is verified using simulations as well as measurements from a 4KB SRAM chip in a 0.13μm technology. It is demonstrated that an SRAM cell state can be preserved at sub-300mV standby VDD, with more than 90% leakage power savings.

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SRAM leakage suppression by minimizing standby supply voltage

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