TY - JOUR
T1 - SRAM Circuits for true random number generation using intrinsic bit instability
AU - Clark, Lawrence T.
AU - Medapuram, Sai Bharadwaj
AU - Kadiyala, Divya Kiran
N1 - Funding Information:
Manuscript received December 22, 2017; revised March 28, 2018; accepted May 6, 2018. Date of publication June 7, 2018; date of current version September 25, 2018. This work was partially supported by the Fujitsu Corporation. (Corresponding author: Lawrence T. Clark.) L. T. Clark and S. B. Medapuram are with the School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: Lawrence.clark@asu.edu; bmedapur@asu.edu).
Publisher Copyright:
© 2018 IEEE.
PY - 2018/10
Y1 - 2018/10
N2 - This paper describes a novel approach to a true random number generator (TRNG) using SRAM circuits. The principles of operation are described in the context of past work on integrated circuit TRNGs. The required modifications to standard SRAM arrays are minor and have little impact on the area. Experimental results from large 1-Mbit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts show good results. Simple helper functions, suitable for very small hardware implementation, allow improvement, including the ability for the resulting binary strings to pass all of the National Institute of Standards randomness tests. We describe the circuits, their principle of operation and statistical behavior, as well as the underlying physical mechanisms providing the entropy.
AB - This paper describes a novel approach to a true random number generator (TRNG) using SRAM circuits. The principles of operation are described in the context of past work on integrated circuit TRNGs. The required modifications to standard SRAM arrays are minor and have little impact on the area. Experimental results from large 1-Mbit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts show good results. Simple helper functions, suitable for very small hardware implementation, allow improvement, including the ability for the resulting binary strings to pass all of the National Institute of Standards randomness tests. We describe the circuits, their principle of operation and statistical behavior, as well as the underlying physical mechanisms providing the entropy.
KW - Physically unclonable functions (PUFs)
KW - random telegraph noise (RTN)
KW - randomness
KW - static random access memory
KW - true random number generation (TRNG)
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U2 - 10.1109/TVLSI.2018.2840049
DO - 10.1109/TVLSI.2018.2840049
M3 - Article
AN - SCOPUS:85048170108
SN - 1063-8210
VL - 26
SP - 2027
EP - 2037
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 10
M1 - 8374983
ER -