SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability

Lawrence T. Clark, Sai Bharadwaj Medapuram, Divya Kiran Kadiyala

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper describes a novel approach to a true random number generator (TRNG) using SRAM circuits. The principles of operation are described in the context of past work on integrated circuit TRNGs. The required modifications to standard SRAM arrays are minor and have little impact on the area. Experimental results from large 1-Mbit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts show good results. Simple helper functions, suitable for very small hardware implementation, allow improvement, including the ability for the resulting binary strings to pass all of the National Institute of Standards randomness tests. We describe the circuits, their principle of operation and statistical behavior, as well as the underlying physical mechanisms providing the entropy.

Original languageEnglish (US)
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOIs
StateAccepted/In press - Jun 6 2018

Fingerprint

Random number generation
Static random access storage
Networks (circuits)
Foundries
Integrated circuits
Entropy
Hardware

Keywords

  • Physically unclonable functions (PUFs)
  • random telegraph noise (RTN)
  • randomness
  • static random access memory
  • true random number generation (TRNG).

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability. / Clark, Lawrence T.; Medapuram, Sai Bharadwaj; Kadiyala, Divya Kiran.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 06.06.2018.

Research output: Contribution to journalArticle

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