SRAM cell optimization for low AVT transistors

Lawrence T. Clark; Samuel Leshner; George Tien

doi:10.1109/ISLPED.2013.6629267

SRAM cell optimization for low AV_T transistors

Lawrence T. Clark, Samuel Leshner, George Tien

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

In this paper, we describe a six-transistor static random access memory (SRAM) cell optimization methodology for transistors with significantly improved matching, while maintaining compatibility with the baseline design. We briefly describe the reduced AV_T transistors and show that they allow substantially improved minimum SRAM operating voltage (V_min) and improved array leakage. Using an efficient design of experiments (DOE) factorial as a pseudo-Monte Carlo generator, points on the tail of the distribution are directly simulated. The highly efficient method is shown to allow optimization and 'what if' scenario investigations. Simulation and silicon results on a 65-nm process as well as simulation results on a 28-nm process are shown.

Original language	English (US)
Title of host publication	Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013
Pages	57-63
Number of pages	7
DOIs	https://doi.org/10.1109/ISLPED.2013.6629267
State	Published - 2013
Externally published	Yes
Event	2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013 - Beijing, China Duration: Sep 4 2013 → Sep 6 2013

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013
Country/Territory	China
City	Beijing
Period	9/4/13 → 9/6/13

Keywords

Low power SRAM
mismatch
statistical design

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/ISLPED.2013.6629267

Cite this

SRAM cell optimization for low AV_T transistors. / Clark, Lawrence T.; Leshner, Samuel; Tien, George.
Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013. 2013. p. 57-63 6629267 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Clark, LT, Leshner, S & Tien, G 2013, SRAM cell optimization for low AV_T transistors. in Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013., 6629267, Proceedings of the International Symposium on Low Power Electronics and Design, pp. 57-63, 2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013, Beijing, China, 9/4/13. https://doi.org/10.1109/ISLPED.2013.6629267

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