Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture

Nishant S. Nukala, Niranjan Kulkarni, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper describes a novel, first of its kind architecture for a threshold logic gate using conventional MOSFETs and an STT-MTJ (Spin Torque Transfer-Magnetic Tunnelling Junction) device. The resulting cell, called STL which is extremely compact can be programmed to realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates. Next, we describe a novel array architecture consisting of STL cells onto which complex logic networks can be mapped. The resulting array, called STLA has several advantages not available with conventional logic. This type of logic (1) is non-volatile, (2) is structurally regular and operates like DRAM, (3) is fully observable and controllable, (4) has zero standby power. These advantages are demonstrated by implementing a 16-bit carry look-ahead adder and compared with two optimized conventional FPGA implementations (Carry Look Ahead Adder and Ripple Carry Adder). The STLA has 12X lower transistor count (compared to CLA-FPGA) and 10X reduction (compared to RCA-FPGA) with comparable energy which will continue to reduce as the STT-MTJ device technology matures.

Original languageEnglish (US)
Title of host publicationProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012
Pages188-195
Number of pages8
StatePublished - 2012
Event2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012 - Amsterdam, Netherlands
Duration: Jul 4 2012Jul 6 2012

Other

Other2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012
CountryNetherlands
CityAmsterdam
Period7/4/127/6/12

Fingerprint

Threshold logic
Magnetoelectronics
Adders
Field programmable gate arrays (FPGA)
Logic gates
Torque
Dynamic random access storage
Transistors

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Nukala, N. S., Kulkarni, N., & Vrudhula, S. (2012). Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012 (pp. 188-195). [6464162]

Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. / Nukala, Nishant S.; Kulkarni, Niranjan; Vrudhula, Sarma.

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012. 2012. p. 188-195 6464162.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nukala, NS, Kulkarni, N & Vrudhula, S 2012, Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. in Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012., 6464162, pp. 188-195, 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012, Amsterdam, Netherlands, 7/4/12.
Nukala NS, Kulkarni N, Vrudhula S. Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012. 2012. p. 188-195. 6464162
Nukala, Nishant S. ; Kulkarni, Niranjan ; Vrudhula, Sarma. / Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012. 2012. pp. 188-195
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