Specifications of nanoscale devices and circuits for neuromorphic computational systems

Bipin Rajendran, Yong Liu, Jae Sun Seo, Kailash Gopalakrishnan, Leland Chang, Daniel J. Friedman, Mark B. Ritter

Research output: Contribution to journalArticle

98 Scopus citations

Abstract

The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations.

Original languageEnglish (US)
Article number6374663
Pages (from-to)246-253
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume60
Issue number1
DOIs
StatePublished - Jan 1 2013

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Keywords

  • CMOS
  • hybrid integrated circuits
  • neural network hardware
  • resistive random access memory (RRAM)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Rajendran, B., Liu, Y., Seo, J. S., Gopalakrishnan, K., Chang, L., Friedman, D. J., & Ritter, M. B. (2013). Specifications of nanoscale devices and circuits for neuromorphic computational systems. IEEE Transactions on Electron Devices, 60(1), 246-253. [6374663]. https://doi.org/10.1109/TED.2012.2227969