Software Coherence Management on Non-coherent Cache Multi-cores

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations


The design complexity and power consumption of hardware cache coherence logic increase considerably with the increase in number of cores. Although skipping coherence can simplify hardware and make it more power-efficient, programming becomes more challenging as programmers have to manually insert DMA instructions to ensure that there is coherence of shared data between cores. To reduce the burden of parallel programming, we propose program transformations and a runtime library that will enable correct execution of data-race-free multi-threaded programs. Our scheme manages coherence at byte granularity rather than conventional page-granularity. We further optimize the performance by introducing the concept of private write notice for each core and combining write notices in our coherence implementation. Experimental results of running multi-threaded signal processing benchmarks on the 8-core non-cache coherent Texas Instruments processor TMS320C6678 demonstrates that our technique achieves 12X performance improvement over naive scheme of disabling caches, and 2X performance improvement over the state-of-art technique.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
PublisherIEEE Computer Society
Number of pages6
ISBN (Print)9781467387002
StatePublished - Mar 16 2016
Event29th International Conference on VLSI Design, VLSID 2016 - Kolkata, India
Duration: Jan 4 2016Jan 8 2016


Other29th International Conference on VLSI Design, VLSID 2016


  • Multi-core Processor
  • Scratchpad Memory
  • Software Coherence Management
  • Software Managed Multicores

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture


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