Soft error reduction in FPGAs for digital I&C in nuclear power plants

Field-programmable gate arrays (FPGAs), due to their advantages in configurability, upgrading and data processing, have been proposed for digital instrumentation and control in nuclear power plants. However, like other integrated circuits, memory-based FPGAs are susceptible to single event effects (SEEs) in the logic and in the memories that program their logic configuration. Downscaling of CMOS technology has led to reduction in load capacitance and drive, which has further increased the problem of SEEs, including multiple bit upsets. Single event upsets (SEUs), a form of SEEs, is a change in state of memory cells that can be caused by terrestrial cosmic neutrons. The aim of our research is to develop fail-proof schemes to curb the effect of SEUs due to neutrons in FPGAs.