TY - GEN
T1 - SODA
T2 - 33rd International Symposium on Computer Architecture, ISCA 2006
AU - Lin, Yuan
AU - LEE, Hyunseok
AU - Woh, Mark
AU - Harel, Yoav
AU - Mahlke, Scott
AU - Mudge, Trevor
AU - Chakrabarti, Chaitali
AU - Flautner, Krisztián
PY - 2006
Y1 - 2006
N2 - The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a minimum. These implementations are time consuming to design and difficult to verify. A programmable hardware platform capable of supporting software implementations of the physical layer, or software defined radio, has a number of advantages. These include support for multiple protocols, faster time-to-market, higher chip volumes, and support for late implementation changes. The challenge is to achieve this without sacrificing power. In this paper, we present a design study for a fully programmable architecture, SODA, that supports software defined radio - a high-end signal processing application. Our design achieves high performance, energy efficiency, and programmability through a combination of features that include single-instruction multiple-data (SIMD) parallelism, and hardware optimized for 16bit computations. The basic processing element is an asymmetric processor consisting of a scalar and SIMD pipeline, and a set of distributed scratchpad memories that are fully managed in software. Results show that a four processor design is capable of meeting the throughput requirements of the W-CDMA and 802.11a protocols, while operating within the strict power constraints of a mobile terminal.
AB - The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a minimum. These implementations are time consuming to design and difficult to verify. A programmable hardware platform capable of supporting software implementations of the physical layer, or software defined radio, has a number of advantages. These include support for multiple protocols, faster time-to-market, higher chip volumes, and support for late implementation changes. The challenge is to achieve this without sacrificing power. In this paper, we present a design study for a fully programmable architecture, SODA, that supports software defined radio - a high-end signal processing application. Our design achieves high performance, energy efficiency, and programmability through a combination of features that include single-instruction multiple-data (SIMD) parallelism, and hardware optimized for 16bit computations. The basic processing element is an asymmetric processor consisting of a scalar and SIMD pipeline, and a set of distributed scratchpad memories that are fully managed in software. Results show that a four processor design is capable of meeting the throughput requirements of the W-CDMA and 802.11a protocols, while operating within the strict power constraints of a mobile terminal.
UR - http://www.scopus.com/inward/record.url?scp=33845875162&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33845875162&partnerID=8YFLogxK
U2 - 10.1109/ISCA.2006.37
DO - 10.1109/ISCA.2006.37
M3 - Conference contribution
AN - SCOPUS:33845875162
SN - 076952608X
SN - 9780769526089
T3 - Proceedings - International Symposium on Computer Architecture
SP - 89
EP - 100
BT - Proceedings - 33rd International Symposium on Computer Architecture,ISCA 2006
Y2 - 17 June 2006 through 21 June 2006
ER -