Smart cache cleaning: Energy efficient vulnerability reduction in embedded processors

Reiley Jeyapaul, Aviral Shrivastava

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

Incessant and rapid technology scaling has brought us to a point where todays, and future transistors are susceptible to transient errors induced by energy carrying particles, called soft errors. Within a processor, the sheer size and nature of data in the caches render it most vulnerable to electrical interferences on static data in the cache. Data in the cache is vulnerable to corruption by soft errors, for the time it remains in the cache. Write-through and earlywrite-back [17] cache configurations reduce the time for vulnerable data in the cache, at the cost of increased memory writes and therefore energy. We propose a smart cache cleaning methodology, that enables copying of only specific vulnerable cache blocks into the memory at chosen times, thereby ensuring data cache protection with minimal memory writes. Our experiments over LINPACK and Livermore benchmarks demonstrate 26% reduced energy-vulnerability product compared to that of hardware cache configurations.

Original languageEnglish (US)
Title of host publicationEmbedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11
Pages105-114
Number of pages10
DOIs
StatePublished - Nov 21 2011
EventEmbedded Systems Week 2011, ESWEEK 2011 - 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11 - Taipei, Taiwan, Province of China
Duration: Oct 9 2011Oct 14 2011

Publication series

NameEmbedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11

Other

OtherEmbedded Systems Week 2011, ESWEEK 2011 - 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11
CountryTaiwan, Province of China
CityTaipei
Period10/9/1110/14/11

Keywords

  • Cache write-back
  • Energy efficient
  • Hybrid technique
  • Smart cache architecture
  • Soft error
  • Vulnerability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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    Jeyapaul, R., & Shrivastava, A. (2011). Smart cache cleaning: Energy efficient vulnerability reduction in embedded processors. In Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11 (pp. 105-114). (Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11). https://doi.org/10.1145/2038698.2038716