Small-world-based Structural Pruning for Efficient FPGA Inference of Deep Neural Networks

Gokul Krishnan, Yufei Ma, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

DNN pruning approaches usually trim model parameters without exploiting the intrinsic graph properties and hardware preferences. As a result, an FPGA accelerator may not directly benefit from such random pruning, with additional cost on indexing and control modules. Inspired by the observation that the brain and real-world networks follow a Small-World model, we propose a graph-based progressive structural pruning technique that integrates local clusters and global sparsity in the Small-World graph and the data locality in the FPGA dataflow. The proposed technique hierarchically trims the DNN into a sparse graph before training, which follows both the Small-World property and FPGA dataflow preferences, such as grouped non-zero and zero parameters to skip data load and corresponding computation. The pruned model is then trained for a given dataset and fine-Tuned to achieve the best accuracy. We evaluate the proposed technique for multiple DNNs with different datasets. It achieves state-of-The-Art sparsity ratio of up to 76% for CIFAR-10, 84% for CIFAR-100, and 76% for the SVHN datasets. Moreover, the generated sparse DNN achieves up to 4× improvement in throughput for an output stationary FPGA architecture across different DNNs with a marginal hardware overhead.

Original languageEnglish (US)
Title of host publication2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings
EditorsShaofeng Yu, Xiaona Zhu, Ting-Ao Tang
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728162355
DOIs
StatePublished - Nov 3 2020
Event15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Virtual, Kunming, China
Duration: Nov 3 2020Nov 6 2020

Publication series

Name2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020 - Proceedings

Conference

Conference15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020
CountryChina
CityVirtual, Kunming
Period11/3/2011/6/20

Keywords

  • Deep Neural Network
  • Graph Efficiency
  • Pruning
  • Small-World graph
  • Sparse FPGA Accelerator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Small-world-based Structural Pruning for Efficient FPGA Inference of Deep Neural Networks'. Together they form a unique fingerprint.

Cite this