Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability

Sayeed A. Badrudduza, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Static random access memories with six and seven transistor cells that maintain full static noise margin during read operation and reside in low leakage voltage collapsed state when unselected are presented. The memory test circuits are fabricated on a 0.13 μm CMOS process technology. The cells are 11% larger than a conventional SRAM cell drawn to the same design rules. Measured test results verify the power, speed, and usable range of power supply voltages for the designs.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages225-228
Number of pages4
ISBN (Print)1424407869, 9781424407866
DOIs
StatePublished - 2007
Event29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States
Duration: Sep 16 2007Sep 19 2007

Other

Other29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
CountryUnited States
CitySan Jose
Period9/16/079/19/07

Fingerprint

Static random access storage
Transistors
Data storage equipment
Electric potential
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Badrudduza, S. A., & Clark, L. T. (2007). Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 225-228). [4405719] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405719

Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability. / Badrudduza, Sayeed A.; Clark, Lawrence T.

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. p. 225-228 4405719.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Badrudduza, SA & Clark, LT 2007, Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability. in Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007., 4405719, Institute of Electrical and Electronics Engineers Inc., pp. 225-228, 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007, San Jose, United States, 9/16/07. https://doi.org/10.1109/CICC.2007.4405719
Badrudduza SA, Clark LT. Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc. 2007. p. 225-228. 4405719 https://doi.org/10.1109/CICC.2007.4405719
Badrudduza, Sayeed A. ; Clark, Lawrence T. / Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability. Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 225-228
@inproceedings{0cd3ea10ed264b81bbbbd0192f0b0c61,
title = "Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability",
abstract = "Static random access memories with six and seven transistor cells that maintain full static noise margin during read operation and reside in low leakage voltage collapsed state when unselected are presented. The memory test circuits are fabricated on a 0.13 μm CMOS process technology. The cells are 11{\%} larger than a conventional SRAM cell drawn to the same design rules. Measured test results verify the power, speed, and usable range of power supply voltages for the designs.",
author = "Badrudduza, {Sayeed A.} and Clark, {Lawrence T.}",
year = "2007",
doi = "10.1109/CICC.2007.4405719",
language = "English (US)",
isbn = "1424407869",
pages = "225--228",
booktitle = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability

AU - Badrudduza, Sayeed A.

AU - Clark, Lawrence T.

PY - 2007

Y1 - 2007

N2 - Static random access memories with six and seven transistor cells that maintain full static noise margin during read operation and reside in low leakage voltage collapsed state when unselected are presented. The memory test circuits are fabricated on a 0.13 μm CMOS process technology. The cells are 11% larger than a conventional SRAM cell drawn to the same design rules. Measured test results verify the power, speed, and usable range of power supply voltages for the designs.

AB - Static random access memories with six and seven transistor cells that maintain full static noise margin during read operation and reside in low leakage voltage collapsed state when unselected are presented. The memory test circuits are fabricated on a 0.13 μm CMOS process technology. The cells are 11% larger than a conventional SRAM cell drawn to the same design rules. Measured test results verify the power, speed, and usable range of power supply voltages for the designs.

UR - http://www.scopus.com/inward/record.url?scp=84938600041&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84938600041&partnerID=8YFLogxK

U2 - 10.1109/CICC.2007.4405719

DO - 10.1109/CICC.2007.4405719

M3 - Conference contribution

AN - SCOPUS:39549111303

SN - 1424407869

SN - 9781424407866

SP - 225

EP - 228

BT - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

PB - Institute of Electrical and Electronics Engineers Inc.

ER -