Six and seven transistor leakage suppressed SRAM cells with improved read stability

Sayeed A. Badrudduza, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Static random access memories with six and seven transistor cells that maintain full static noise margin during read operation and reside in low leakage voltage collapsed state when unselected are presented. The memory test circuits are fabricated on a 0.13 μm CMOS process technology. The cells are 11% larger than a conventional SRAM cell drawn to the same design rules. Measured test results verify the power, speed, and usable range of power supply voltages for the designs.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages225-228
Number of pages4
ISBN (Print)1424407869, 9781424407866
DOIs
StatePublished - Jan 1 2007
Event2007 IEEE Custom Integrated Circuits Conference, CICC - San Jose, CA, United States
Duration: Sep 16 2007Sep 19 2007

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

Conference2007 IEEE Custom Integrated Circuits Conference, CICC
CountryUnited States
CitySan Jose, CA
Period9/16/079/19/07

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Badrudduza, S. A., & Clark, L. T. (2007). Six and seven transistor leakage suppressed SRAM cells with improved read stability. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC (pp. 225-228). [4405719] (Proceedings of the Custom Integrated Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405719