TY - GEN
T1 - Single-Phase Active-Clamped Isolated SEPIC PFC Converter with Partial Power Processing Output Stage
AU - Wu, Deliang
AU - Ayyanar, Raja
N1 - Funding Information:
ACKNOWLEDGMENT This work was partly supported by the Office of Energy Efficiency and Renewable Energy, U.S. Department of Energy with North Carolina State University, PowerAmerica Institute, under Award DE-EE0006521.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/3
Y1 - 2020/3
N2 - A single-phase, single-stage, isolated active-clamped SEPIC PFC converter with a partial power processing (PPP) output stage is presented. The PPP stage is implemented with an extra winding in the isolation transformer, low voltage rating diode and MOSFET and a series coupling capacitor. This converter features zero-voltage switching (ZVS) for the main switch and the clamp switch in the main power stage, and zero- current switching (ZCS) for the auxiliary switch in the PPP stage. The output PPP stage enables output voltage regulation, double line frequency ripple cancellation and fast dynamic response for the output voltage. The double line frequency ripple in the output voltage is reduced significantly with the PPP stage, which translates into significant output filter capacitance reduction and power density improvement for the single-phase PFC converter. The performance of the proposed converter is verified with experimental results.
AB - A single-phase, single-stage, isolated active-clamped SEPIC PFC converter with a partial power processing (PPP) output stage is presented. The PPP stage is implemented with an extra winding in the isolation transformer, low voltage rating diode and MOSFET and a series coupling capacitor. This converter features zero-voltage switching (ZVS) for the main switch and the clamp switch in the main power stage, and zero- current switching (ZCS) for the auxiliary switch in the PPP stage. The output PPP stage enables output voltage regulation, double line frequency ripple cancellation and fast dynamic response for the output voltage. The double line frequency ripple in the output voltage is reduced significantly with the PPP stage, which translates into significant output filter capacitance reduction and power density improvement for the single-phase PFC converter. The performance of the proposed converter is verified with experimental results.
KW - SEPIC
KW - Single-phase PFC
KW - ZCS
KW - ZVS
KW - partial power processing
KW - power decoupling
UR - http://www.scopus.com/inward/record.url?scp=85087782266&partnerID=8YFLogxK
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U2 - 10.1109/APEC39645.2020.9124282
DO - 10.1109/APEC39645.2020.9124282
M3 - Conference contribution
AN - SCOPUS:85087782266
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 1285
EP - 1291
BT - APEC 2020 - 35th Annual IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2020
Y2 - 15 March 2020 through 19 March 2020
ER -