TY - GEN
T1 - Single event transient mitigation in cache memory using transient error checking circuits
AU - Yao, Xiaoyin
AU - Clark, Lawrence T.
AU - Patterson, Dan W.
AU - Holbert, Keith
PY - 2010
Y1 - 2010
N2 - Protecting a high performance radiation hardened by design (RHBD) cache from single-event transient (SET) induced peripheral circuit errors is presented. Cache memory holds processor architectural state and peripheral errors can cause incorrect operations that affect entire data words, including parity. Thus, a periphery circuit, e.g., word-line, error can be induced that results in silent data corruption, for instance by writing two locations at once. The design presented here includes checking circuits to detect potential SET induced errors, allowing mitigation by invalidation of the write-through cache blocks. A 16 kB cache and test engine, fabricated on an IBM 90 nm bulk CMOS process, irradiated with heavy ions, is used to provide experimental validation of the design.
AB - Protecting a high performance radiation hardened by design (RHBD) cache from single-event transient (SET) induced peripheral circuit errors is presented. Cache memory holds processor architectural state and peripheral errors can cause incorrect operations that affect entire data words, including parity. Thus, a periphery circuit, e.g., word-line, error can be induced that results in silent data corruption, for instance by writing two locations at once. The design presented here includes checking circuits to detect potential SET induced errors, allowing mitigation by invalidation of the write-through cache blocks. A 16 kB cache and test engine, fabricated on an IBM 90 nm bulk CMOS process, irradiated with heavy ions, is used to provide experimental validation of the design.
KW - CMOS memory integrated circuits
KW - Heavy ion beams
KW - High-speed integrated circuits
KW - Radiation hardening
UR - http://www.scopus.com/inward/record.url?scp=78649865546&partnerID=8YFLogxK
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U2 - 10.1109/CICC.2010.5617439
DO - 10.1109/CICC.2010.5617439
M3 - Conference contribution
AN - SCOPUS:78649865546
SN - 9781424457588
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - IEEE Custom Integrated Circuits Conference 2010, CICC 2010
T2 - 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
Y2 - 19 September 2010 through 22 September 2010
ER -