Single-chip, asynchronous echo canceller for high-speed data communication

Richard P. Mackey; Jeffrey J. Rodriguez; Jo Dale Carothers; Sarma B K Vrudhula

Single-chip, asynchronous echo canceller for high-speed data communication

Richard P. Mackey, Jeffrey J. Rodriguez, Jo Dale Carothers, Sarma B K Vrudhula

Computing and Augmented Intelligence, School of (IAFSE-SCAI)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.

Original language	English (US)
Title of host publication	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Publisher	IEEE
Pages	181-184
Number of pages	4
State	Published - 1995
Event	Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA Duration: Sep 18 1995 → Sep 22 1995

Other

Other	Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit
City	Austin, TX, USA
Period	9/18/95 → 9/22/95

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@inproceedings{11e8fa1213bd454c823b3ec73a8b583d,

title = "Single-chip, asynchronous echo canceller for high-speed data communication",

abstract = "A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.",

author = "Mackey, {Richard P.} and Rodriguez, {Jeffrey J.} and Carothers, {Jo Dale} and Vrudhula, {Sarma B K}",

year = "1995",

language = "English (US)",

pages = "181--184",

booktitle = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

publisher = "IEEE",

note = "Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit ; Conference date: 18-09-1995 Through 22-09-1995",

}

TY - GEN

T1 - Single-chip, asynchronous echo canceller for high-speed data communication

AU - Mackey, Richard P.

AU - Rodriguez, Jeffrey J.

AU - Carothers, Jo Dale

AU - Vrudhula, Sarma B K

PY - 1995

Y1 - 1995

N2 - A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.

AB - A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.

UR - http://www.scopus.com/inward/record.url?scp=0029539521&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029539521&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0029539521

SP - 181

EP - 184

BT - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

PB - IEEE

T2 - Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit

Y2 - 18 September 1995 through 22 September 1995

ER -

Single-chip, asynchronous echo canceller for high-speed data communication

Abstract

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ASJC Scopus subject areas

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