Single-chip, asynchronous echo canceller for high-speed data communication

Richard P. Mackey, Jeffrey J. Rodriguez, Jo Dale Carothers, Sarma B K Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz.

Original languageEnglish (US)
Title of host publicationProceedings of the Annual IEEE International ASIC Conference and Exhibit
PublisherIEEE
Pages181-184
Number of pages4
StatePublished - 1995
Externally publishedYes
EventProceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA
Duration: Sep 18 1995Sep 22 1995

Other

OtherProceedings of the 8th Annual IEEE International ASIC Conference and Exhibit
CityAustin, TX, USA
Period9/18/959/22/95

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Mackey, R. P., Rodriguez, J. J., Carothers, J. D., & Vrudhula, S. B. K. (1995). Single-chip, asynchronous echo canceller for high-speed data communication. In Proceedings of the Annual IEEE International ASIC Conference and Exhibit (pp. 181-184). IEEE.