Simulation of the impact of process variation on the optimized 10-nm FinFET

We examined the influence of process variation on device performance of the optimized 10-nm FinFET device using a fully self-consistent quantum-mechanical transport simulator based on the contact block reduction method. Sensitivity of the on-current, leakage currents, threshold voltage, drain-induced barrier lowering, and subthreshold swing for the optimized FinFET to process variation at room temperature have been investigated. Subthreshold source-to-drain leakage current is found to be the most sensitive parameter to process variation. Gate leakage current has been analyzed for both poly-Si gates and gates with the work function of 4.35 eV. For poly-Si gates, the gate leakage is found to influence the subthreshold swing below or at a gate oxide thickness of 1 nm. Device performance has also been analyzed at "slow process" corner to estimate the worst case degradation in performance matrices of the considered nano-FinFET.